category: Top Stories

category: Auto, Security & Edge AI

DFM And Multipatterning
By Ed Sperling - 17 Jul, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss DFM at advanced nodes with Kuang-Kuo Lin, director of foundry design enablement at Samsung Electronics; Jongwook Kye, lithography modeling and architecture fellow at GlobalFoundries; David Abercrombie, advanced physical verification methodology program manager at Mentor Graphics; Ya-Chieh Lai, engineering director for DFM/CLS silicon signoff and ver... » read more

What Happened To 450mm?
By The SE Staff - 17 Jul, 2014 - Comments: 1

By Mark LaPedus, Ed Sperling & Katherine Derbyshire There was a time not very long ago—one process node, in fact—when the economic momentum of Moore’s Law seemed unstoppable with a combination of extreme ultraviolet lithography, larger wafer sizes and a variety of new materials. Shrinking feature sizes is still technically possible, but certainly not with the same promised economic benef... » read more

How To Lower LED Costs
By Mark LaPedus - 17 Jul, 2014 - Comments: 2

The LED market remains hot, particularly in the solid-state lighting segment. In fact, solid-state lighting continues to expand amid a precipitous drop in LED prices. And LEDs are expanding into new fronts, such as automotive and intelligent lighting. The LED boom hasn’t been fun for all parties, however. Amid pressure to reduce their tool costs, LED equipment makers are still in the mids... » read more

Will 7nm And 5nm Really Happen?
By Mark LaPedus - 14 Jul, 2014 - Comments: 2

Today’s silicon-based finFETs could run out of steam at 10nm. If or when chipmakers move beyond 10nm, IC vendors will require a new transistor architecture. III-V finFETs, gate-all-around FETs, quantum well finFETs, SOI finFETs and vertical nanowires are just a few of the future transistor candidates at 7nm and 5nm. Technically, it’s possible to manufacture the transistor portions of the... » read more

After Moore’s Law: More With Less
By Brian Bailey - 10 Jul, 2014 - Comments: 6

In the decades when Moore’s Law went unquestioned, the industry was able to migrate to the next smaller node and receive access to more devices that could be used for increased functionality and additional integration. While less significant transistor-level power savings have been seen from the more recent nodes, as leakage currents have increased, the additional levels of integration have b... » read more

Raising The Abstraction Of Power: Trends
By Ann Mutschler - 10 Jul, 2014 - Comments: 0

Given that design requirements for today’s SoCs go well beyond performance and area, energy efficiency and its impact on system design plays a major role for many end applications ranging from wireless sensor networks to autonomous vehicles as well as emerging applications in the Internet of Things market segment, where cooling capability is limited and expensive. For these reasons, a comp... » read more

IP And FinFETs At Advanced Nodes
By Ed Sperling - 10 Jul, 2014 - Comments: 2

Semiconductor Engineering sat down to discuss IP and finFETs at advanced nodes with Bernard Murphy, CTO of Atrenta; Warren Savage, president and CEO of IPextreme; Aveek Sarkar, vice president of engineering and product support at Ansys-Apache; Randy Smith, vice president of marketing at Sonics. What follows are excerpts of that conversation. SE: As we push into the next nodes, we’ve got a ... » read more

Supporting LP In New Process Nodes
By Ann Mutschler - 10 Jul, 2014 - Comments: 0

Manufacturing process nodes and EDA tools are advancing all the time, but not always utilized at the same pace. And from a tools perspective, there are challenges to supporting low power in new process nodes while maintaining and improving the existing process nodes. One way design teams address this is by leveraging the most advanced software on the less-than-bleeding edge designs. To th... » read more

Stacked Die Are Coming Soon. Really
By Ed Sperling - 10 Jul, 2014 - Comments: 3

Since the beginning of the decade there have been many predictions that stacked die were just over the hill, but the time it has taken to climb that hill has been longer than most people would have anticipated. In fact, TSMC has been fully capable of building stacked die since last year, with risk production expected to be completed by year, according to Gartner. But something very fundament... » read more

28nm FinFETs?
By Brian Bailey - 10 Jul, 2014 - Comments: 5

One star of the upcoming 14/16nm process node is the introduction of the finFET, a fundamentally new transistor that overcomes many of the limitations associated with planar transistors. While these devices are more complex to construct—and the physical extraction processes associated with them is more complex due to an increased number of resistances and capacitances—they are seen as a tra... » read more

← Older posts Newer posts →

  • Sponsors

  • Standards/Organizations

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy