category: Top Stories

category: Auto, Security & Edge AI

Cost Per Transistor Gets Fuzzier
By Ed Sperling - 31 Jan, 2013 - Comments: 0

By Ed Sperling Cost per transistor always has been a major reason for chipmakers to migrate to the next process node. By shrinking transistors and adding more logic, performance usually gets a boost. Moreover, that usually provides enough engineering wiggle room to add some improvements in energy efficiency. The basic assumption that you can double the number of transistors every 24 months,... » read more

Changes In The Supply Chain
By Ed Sperling - 31 Jan, 2013 - Comments: 0

Runaway complexity in design, implementation, verification and manufacturing is being mirrored across an increasingly complex supply chain. Now the question is what to do about it. Complexity is being driven by the continued shrinking of feature sizes and the clamor for more functionality to leverage the real estate that becomes available with each new process node. But the increased density... » read more

Supersizing Wafers
By Ed Sperling - 24 Jan, 2013 - Comments: 0

By Katherine Derbyshire Get ready for 450mm wafers. First seriously considered in 2005, these supersized wafers, along with the equipment to handle, measure, and process them, have gradually made their way to the top of the semiconductor industry’s priority list. But what exactly does that mean? What will 450mm fabs look like, and how will they differ from the 300-mm fabs being built toda... » read more

What Will Replace Dual Damascene?
By Mark LaPedus - 24 Jan, 2013 - Comments: 0

By Mark LaPedus In the mid-1990s, IBM announced the world’s first devices using a copper dual damascene process. At the time, the dual damascene manufacturing process was hailed as a major breakthrough. The new copper process enabled IC makers to scale the tiny interconnects in a device, as the previous material, aluminum, faced some major limitations. Dual damascene remains the workhorse... » read more

Inside The Package
By Mark LaPedus - 24 Jan, 2013 - Comments: 0

By Mark LaPedus Semiconductor Manufacturing & Design sat down to discuss IC packaging trends with Rich Rice, senior vice president for North America at Taiwan’s Advanced Semiconductor Engineering (ASE), the world’s largest independent IC packaging and test house. SMD: Amazingly, there are still more than 100 vendors competing in the IC test and assembly business today. But for year... » read more

Reducing The Drama In DFM
By Ed Sperling - 24 Jan, 2013 - Comments: 0

By Ann Steffora Mutschler For reducing cycle time of DFM checks prior to manufacturing, pattern matching is a topic of great excitement as of the past few manufacturing nodes. The idea behind the technology is that there are certain patterns in the physical layout of the chip, which unless they are addressed, won’t come out right. That’s what causes the drama, observed Saleem Haider, se... » read more

Smartphones Dial Up New RF Processes
By Mark LaPedus - 24 Jan, 2013 - Comments: 0

By Mark LaPedus The rapid shift towards smartphones and tablets is driving the need for new and low-power chips at finer geometries. Today, the latest application processors, integrated basebands and other digital cell-phone chips are 28nm planar devices. And it won’t be long before OEMs incorporate 20nm planar and finFET devices in their systems as a means to reduce power and extend batt... » read more

Stacked Die From A Networking Angle
By Mark LaPedus - 24 Jan, 2013 - Comments: 1

By Mark LaPedus The first wave of 2.5D chips using silicon interposers are trickling out in the marketplace.FPGA vendor Xilinx was the first chipmaker to ship a 2.5D device, and Altera, Cisco, Huawei and IBM recently have talked about their respective 2.5D chip developments. Generally, Altera and Xilinx have taken a somewhat identical and straightforward approach. The two companies are sepa... » read more

Tradeoffs On The Fly
By Ed Sperling - 17 Jan, 2013 - Comments: 0

By Ann Steffora Mutschler With classical bulk planar technology no longer shrinkable, the industry has been honing in on new ways to continue some scaling, achieve extra speed or better power while minimizing leakage. “To overcome the limits [of bulk planar technology] we need a different solution,” explained Giorgio Cesano, technology R&D marketing director at STMicroelectron... » read more

It’s Transition Time Again
By Ed Sperling - 17 Jan, 2013 - Comments: 0

By Ed Sperling After decades of shrinking features, developing new software on every level and engineering huge improvements in energy efficiency and performance, the semiconductor industry has reached a crossroads. To get to the next level will require massive improvements on all fronts, but not all consumers will be willing to pay for them. For example, if a battery lasts an entire day f... » read more

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