Metrology Options Increase As Device Needs Shift

Semiconductor fabs are taking an ‘all hands on deck’ approach to solving tough metrology and yield management challenges, combining tools, processes, and other technologies as the chip industry transitions to nanosheet transistors on the front end and heterogenous integration on the back end.

Optical and e-beam tools are being extended, while X-ray inspection is being added on a case-by-case basis. And for new processes like nanosheet transistor fabrication and deep-trench metrology, alternative methods like Raman spectroscopy, SIMS, and mass metrology are coming into play.

Inflection points
Semiconductor processing is in the midst of several key inflection points — a transition to EUV and ultimately high-NA EUV patterning, the use of 3D structures for high-density storage, nanosheet transistors, and heterogenous integration.

“All of those inflections create some pretty significant challenges at the metrology level. First, dimensions are much smaller, so we’re going to need metrology with much higher sensitivity and precision,” said David Fried, corporate vice president of computational products at Lam Research. “Secondly, the increasing number of high-aspect-ratio designs with hidden structures creates more opportunity for excursion and risk.”

There is an increasing need for hybrid metrology, according to Fried, bringing together disparate techniques to gain an understanding of what is happening at the process and device level. Modeling and virtual manufacturing also will play key roles in both defect and dimensional metrology.

Others agree. “The key is dimensional metrology, and we’re really looking at complex 3D structures,” said Shay Wolfling, CTO of Nova. “It started with 3D NAND. Now, in nanosheet FETs, customers are really interested in controlling each individual nanosheet in, for instance, three nanosheets. And if you look at the roadmap, it will go to even more nanosheets, and eventually CFETs, so it’s only getting more challenging.”

Gate-all-around transistors
GAA transistors, also called nanosheet FETs, are being used by leading chip manufacturers at the 3nm (Samsung) and 2nm (TSMC and Intel) nodes, with contacted gate pitch extending to 40nm and metal pitches dipping below 30nm. Bringing these advanced 3D structures from R&D into manufacturing requires fast, non-destructive measurement methods with fast cycles of learning and as little dependence on off-line techniques as possible.

A recent analysis by IBM of the various steps in nanosheet transistor fabrication and the likely metrology tools for implementation pointed to changes that coincide with the rollout of gate-all-around transistors. “Nanosheet technology may be when some offline techniques transition from lab to the fab, as certain critical measurements need to be monitored in real time.” [1]

Optical remains strong
The IBM engineers highlighted the use of measurement methods, including OCD (scatterometry), CD-SEM, AFM, Raman, XRD and XRF (x-ray diffraction and fluorescence), and VC-SEM (voltage contrast SEM). Both OCD and CD-SEM are widely used throughout semiconductor manufacturing, a trend that is expected to continue. Perhaps a combination of scatterometry and top-down CD-SEM may be used to measure fin width, but the study highlighted that more work is needed to characterize nanosheet and fin structures. The different stochastic effects in metrology, including line roughness, local CD variation, edge placement and overlay errors as well as missing or bridged features, significantly affect yield and device performance. [2]

Optical-based methods provide the fastest means of in-line inspection and metrology. Optical CD measurements (OCD, a.k.a. scatterometry) are not a direct measurement of film thicknesses and require modeling and reference methods to correlate to actual values. The OCD measurements typically take place on grating targets positioned on the scribe line of the wafer. KLA, Applied Materials, Onto Innovation, and Nova provide leading OCD solutions.

The optical solution from Onto Innovation uses a combination of spectroscopic reflectometry and ellipsometry with an AI-based engine called AI-Diffract to analyze the different layers in nanosheet transistors. This approach is designed to provide superior layer contrast versus traditional OCD systems. In addition, machine learning is playing an increasing role in OCD dimensional analyses, building on the long used physical models for OCD.

Nova has its own flavor of OCD, Spectral Interferometry, which combines the full data of scatterometry with the complete wavefront of the reflected light. When this is performed over multiple wavelengths, the method allows “focusing” of the spectral information, ignoring the contribution of underlayers and allowing better performance on the parameters of interest. For instance, subtle metal line differences in the interconnects can be measured without the need to consider the underlying transistor layers.

Mass metrology
Mass metrology is a non-destructive method that enables quantification of high aspect ratio trenches in applications where conventional metrology is insufficient. “In some of the advanced memories, DRAM and NAND, the interesting thing is you’re etching trillions of them on a wafer,” said Fried. “The amount of mass you remove in these etches is pretty significant, which is why mass metrology works so well.”

This is one of the techniques being evaluated for nanosheet processes (see figure 1). A second example looks at mass metrology for measuring trench dimensions.

OCD effectively measures trench depth, and CD-SEM measures top CD, but direct measurement of bottom CD proves difficult, according to engineers at Infineon. [3] They used OCD, CD-SEM, and Metryx mass metrology from Lam Research, to determine trench bottom width in 42µm deep trenches (6.75µm pitch) before and after etching. The study found linear relationships between bottom CD from mass loss and scatterometry. There was also excellent correlation between mass loss and CD-SEM cross-sectional measurements. “The mass loss method is capable of monitoring the stability of the etch process and provides quantitative information on the geometry of deep trenches,” the engineers concluded.

Fig. 1: Mass metrology detects an outlier in nanosheet spacer etchback. Source: Lam Research

X-ray inspection

Fig. 2: X-ray inspection (top) and analytics (bottom) identifies “dead” areas due to stacking faults, threading dislocations, and micropipes in the lattice. Source: Bruker

One area where X-ray inspection provides defectivity analysis is in power ICs, specifically GaN-on-SiC wafers (see figure 2). SiC wafers must be inspected for various types of defects, including micropipes and threading dislocations in the lattice, often along the basal plane of the wafer (basal defects). Such defects can range in size from the angstrom level to several hundred nanometers, and can lead to device failure or rejection of the SiC wafer itself.

Raman spectroscopy is a bright spot when it comes to germanium composition measurement and it can provide inline SiGe strain analysis, an essential factor in transistor performance. However, a depth-dependent reading of concentration is more difficult to obtain with Raman, and may be an area where SIMS (secondary ion mass spectroscopy) comes into play.

SIMS provides chemical composition information, using a sputtered ion beam and measuring the ejected secondary ions from the wafer. The output is viewed as depth uniformity (see figure 3) uniformity of germanium concentration at different points on the wafer (see figure 4).

Fig. 3: Germanium depth profile in SiGe layer. Source: Nova

Fig. 4: In-line SIMS of germanium concentration based on 9-point wafer measurements. Source: Nova

BEOL metrology
“An important part of all the inspection and metrology is we need to some extent customize the system for the application,” noted Tim Skunes, vice president of research and development, Nordson Test & Inspection’s CyberOptics portfolio. The need to manufacture millions of microbumps at high yield has led to 100% inspection methods. “We need to know what the customer is looking for. In a simple case, if it’s a bump measurements, the customer want to inspect 10 million bumps and make sure we give them all the outliers — the tallest bump, the shortest bump, and average, three sigma, etc. When a defective bump is found, they want to know all the details, the type of physical damage, etc., so they can do rapid failure analysis.” A 3 micron optical MRS sensor is integrated into the CyberOptics inspection and metrology systems for these applications

In these cases, copper pillar bumps have become very common, essentially tall pillars with rounded silver-tin solder tips. Another quality check is provided by X-ray diffraction and XRF. “The biggest things we measure with XRF are thickness and the composition of alloys. Measuring solder composition, we look at things like RDL and UBM film thickness — silver content in bumps, for instance — and look for voids or bridging defects within 3D packaging. Consistency is the key thing — making sure the RDL has the right alloy composition,” said Paul Ryan, vice president and general manager of Bruker’s X-ray Division.

Conclusion
OCD and CD-SEM methods are being extended to meet the needs of nanosheet transistors, but the challenge of deep structures and hidden features continues to challenge metrology methods. Alternatives such as X-ray, Raman, SIMS, and mass metrology are carving out their respective niches as chipmakers make their way to high-volume manufacturing at the 5nm and 3nm nodes.

References

1. Breton, “Review of Nanosheet Metrology Opportunities for Technology Readiness,” J. Micro/Nanopatterning, Materials, and Metrology, Vol 21, Issue 2, 021206 (April 2022), https://doi.org/10.1117/1.JMM.21.021206.
2. Peters, “Strategies for Faster Ramps on 5nm Chips,” Semiconductor Engineering, April 12, 2022, https://semiengineering.com/strategies-for-faster-yield-ramps-on-5nm-chips/
3. Haberjahn, et.al., “Combination of Mass Metrology with Scatterometry to Obtain Bottom Width of Deep Trenches,” IEEE Advanced Semiconductor Manufacturing Conference (ASMC), May 2022, https://ieeexplore.ieee.org/document/9792504