More Manufacturing Issues, More Testing

Douglas Lefever, CEO of Advantest America, sat down with Semiconductor Engineering to talk about changes in test, the impact of advanced packaging, and business changes that are happening across the flow. What follows are excerpts of that discussion.

SE: What are the big changes ahead in test?

Lefever: It’s less about inflection points and more like moving from algebra to calculus in the back-end. From an industry standpoint, the back-end has to look a lot more like the front-end. That resonates with a lot of customers, particularly with the adoption of advanced packaging. It’s a slightly more complex level of test, and definitely more testing is required. A lot has been written about shifting left and known-good die (KGD), and as you get into advanced packaging and chiplets, having that test coverage further upstream is more important. All the challenges of actually doing that are engineering problems that have to be solved. So there are more system-level tests (SLTs), which is pushing right. But then there’s a conflation of those two, where we need to do some SLT further upstream at the wafer level. Those concepts have been around for awhile. It’s more about executing on some of the things that we’ve been looking at for 5 to 10 years.

SE: Is this blurring the lines between front- and back-end? We’re now seeing testing at multiple insertion points throughout the flow.

Lefever: Yes, and those insertion points move around, depending on the type of device and where you are in the lifecycle of that device. Ideally, you want to get yield data at the wafer level, but that can be difficult. And then as things mature, less test is used, or maybe more burn-in is added, because you haven’t got sufficient reliability. The test flows that happen throughout the lifecycle of the device are constantly shifting.

SE: There’s a lot of diversity in the market. We are seeing chiplets and various types of advanced packaging, advanced-node manufacturing at three foundries, and lots of activity at older nodes. There also are new materials to test, and specialty foundries cropping up. How does that affect your strategy going forward?

Lefever: We typically are focused on the high-volume, higher-end part of the market, because it’s a better business for the company. We cover that first and foremost. And then, when it comes to more low-volume niche areas, we look at whether we should develop a specific instrument to attack that area. There are some areas, particularly vehicle electrification, that start out as niches and then grow. Those include some of the higher voltage requirements needed for silicon carbide applications in vehicles, and that’s been around for a long time.

SE: There’s probably one application that’s doing the billion units these days, and the rest of it is now all scattered into lots of different pieces, increasing diversity, and more customization. What kind of impact does that have on test?

Lefever: The AT industry has largely moved to scalable platforms, where you’re always going to need some level of power supplies and digital cards. We tried to develop those so that they’re kind of multi-purpose and can be utilized across many of these different kinds of applications, be it low-volume, high-volume, or specific niche areas. And then we have the ability to do additional instrumentation for a specific type. We usually don’t have trouble with digital applications versus mixed signal or RF. We have universal analog pins, and our digital cards have a range of speeds.

SE: Do materials like SiC and GaN require anything different?

Lefever: We’re doing things like battery management, which we can cover with our mixed signal configurations and our integrated power solutions. But there are some areas where different kinds of methodologies are required, such as for really high voltage kinds of test applications.

SE: Test is taking longer because there’s more emphasis on reliability, and because the chips themselves are more valuable when they’re developed at advanced nodes or are in advanced packages. How does that affect test?

Lefever: There are a lot more tests and more insertions, different temperature profiling, and more active control during system-level test to run it through its native application. You’re seeing now a lot more on chip sensors and agents being deployed. So it’s a wide array of things. The data center guys have now shifted and increased the DPM (defects per million) requirements back to the CPU players, which has driven a ton more test requirements by the big CPU players.

SE: It also changes the economics of test fairly significantly, because back in the 1990s, chipmakers did not want tests to account for any more than 2% of the total development cost. Now, with reliability and the value of the chips going up, is it still 2%? Or has that been thrown out the window and it’s now, ‘Get the job done, no matter what?’

Lefever: It’s more the latter today. The capital intensity for AT has fluctuated over the years. I’ve seen it as high as 4%, and it’s been down as low as 1%. It depends on the segment you’re talking about. In the HPC/AI area, it’s probably on the higher end of where it was almost was 20 or 30 years ago. But structural testing in lots of cases is not sufficient anymore. So you need balanced functional tests in addition to the structural test. And you need some degree of system-level tests to really guarantee coverage. For the most part, you need more tests with these high-end chips. They’re so expensive that the industry easily justifies more tests to make sure that you don’t have any kind of problems out in the field, especially when there are competitive situations and market-share movements like there are right now between the big players. They want to make sure that quality is maintained. That doesn’t mean we don’t get complaints. But at the end of the day, when they sit down and look at it, more tests are absolutely worth the investment for what they get in return.

SE: Is your R&D as a percentage of revenue going up as well, or does that stay flat?

Lefever: We have historically been in that 15% area. Because our revenue has grown so fast in the last couple of years, we’re probably going to be challenged to keep that percentage. It’s impossible to hire and even spend the money needed to keep that percentage. But we don’t say we have to be at a certain percentage. We’re more concerned with, ‘What do we need?’

SE: So what do you need to invest in?

Lefever: There are a lot of areas. We continue to invest in the RF area, moving from 5G to 6G, as we move into even the higher frequency areas. That’s a lot of big ‘R’, little ‘d.’ Advantest always has taken an approach of investing in custom silicon to do our test processors and our driver comparator ASICs. We still feel that is a valuable approach, but it also requires a lot of investment in design and in the silicon to keep pace with the test requirements. We’ll be investing a lot in chip design. The whole 3D approach adds more requirements for packaging, together with known good die at the wafer level. That adds a lot of challenges. We’re investing a lot in thermal control solutions that can be coupled with our tester.

SE: 3D can mean different things. Which 3D are you looking at?

Lefever: It’s the true implementation. We’re already into 2.5 and 3D, and have been for a long time. But eventually we’re getting into 3D-IC with hybrid bonding, and where dies are being stacked. When that is fully implemented, it will add tough challenges. Across the test industry, things have have been disaggregated with the material handler at with the prober, versus the probe card, versus the tester, and everything in between. There has to be a little bit more of a holistic approach for truly doing KGD for these high-power solutions that are then going to be coupled with other chips in a package. And there will be partnerships and a lot of things that we work out with customers.

SE: How about chiplets?

Lefever: That’s perfect for us. The analytics part is going to be a big component. We’re just a piece of that. The goal is to have traceability, so when there are problems you have the feedback and can trace that all the way back to whatever fab they’re coming from. Test is going to play a big role in data acquisition and feeding that back together with analytics.

SE: What’s happens with AI in the testing process?

Lefever: We released something we call ACS Edge, which is an edge box. It’s being deployed now, and people are using it. There has always been a problem with the tester having the capability within its host controller. When you add kind of a supercomputer alongside the tester, you open up all of this compute power, and you can start looking at doing kind of real-time adaptive test using that edge compute box. Containers with algorithms get sent down from a container hub. Those algorithms get updated by the customers, or we deploy use cases in those models. This is a big trend right now. It’s going to solve a lot of problems and limitations that the current AT architectures have. We want to deploy not just across our AT, but the other types of test insertions, be it burn-in or SLT or post-silicon validation. It opens the door for a lot of more sophisticated use cases.

SE: It also changes the dynamics for what you consider to be coverage, right? In the past, it was always about parallelizing more operations. Now you’re trying to add a bit of intelligence into how you sort this stuff, as well.

Lefever: That’s right, and so you can change the test program on the fly, and the data is streaming off the device to the tester, and those algorithms with 10 milliseconds of latency can alter a test program for the very next die or within the same die or package. People have done adaptive test for a long time, or called it that. This is the realization of true on-the-fly adaptive test.

SE: Are you getting called on to perform different functions than in the past?

Lefever: Yes, the industry is going back and mixing functional tests more with structural tests, and at the same time that more DFT that is being added. More scan, serial high-speed scan over USB or PCIe ports are being used, but still that’s not enough, so system level testing is continuing to be deployed.

SE: Can you get enough talent to make all of this work, or do you need to do acquisitions?

Lefever: There is some of that. There are a lot of good small companies that don’t have really the ability to scale, because it’s heavily dependent on R&D and placing bets. So they run out of gas. Occasionally, we look for opportunities where there are entire teams we can pick up. We recently made an acquisition of an entire engineering team that became available as a result of a divestment by another company. In the U.S., we’ve made several acquisitions in the past the last couple of years motivated by the strategic product synergies, but those acquisitions have led to a lot of new talent for Advantest.