Standardizing Chiplet Interconnects

The chip industry is making progress on standardizing the infrastructure for chiplets, setting the stage for faster and more predictable integration of different functions and features from different vendors.

The ability to choose from a menu of small, highly specialized chips, and to mix and match them for specific applications and use cases, has been on the horizon for more than a decade. But the idea of integrating hard IP into a package really began gaining steam after the International Technology Roadmap for Semiconductors ended in 2016. Since then, chipmakers have been looking at a variety of different options to supplement scaling, which has become increasingly expensive at each new node below 22nm.

Chiplets have emerged as a way of extending Moore’s Law, or sidestepping it entirely, depending upon the application. Either way, the recent introduction of the Universal Chiplet Interconnect Express (UCIe) Specification 1.0 is an enabling technology, providing a standard way to connect these limited function/feature chiplets together into a semi-customized package.

UCIe follows a similar approach as the Peripheral Component Interconnect Express (PCIe), a standardized interface for PCBs that enables vendors to mix and match various devices for functions such as graphics, memory, and storage. UCIe brings that down to the level of die-to-die interconnects, and it has the backing of such industry heavyweights as AMD, Arm, ASE, Google, Intel, Meta, Microsoft, Qualcomm, Samsung, and TSMC.

The ultimate goal is to create a large ecosystem or marketplace for chiplets, which can be quickly assembled using pre-characterized, off-the-shelf components. From a manufacturing standpoint, chiplets provide faster time to yield because they are physically smaller than SoCs. The hard part is integrating devices into a package that were developed by multiple vendors with predictable results. This is where UCIe plays a pivotal role.

“Standardized interconnect protocols like UCIe can serve as key enablers for a robust ecosystem for chiplet technologies,” said Gordon Allan, verification IP product manager for the IC Verification division of Siemens EDA. “In turn, this ecosystem can enable higher productivity and faster time to market, in addition to the inherent die yield benefits that come with disaggregation. Although UCIe itself does not increase die yield, the use of chiplets creates the opportunity for increased yield due to their smaller size and the opportunity to be implemented at the ideal node point for their function.”

UCIe benefits
Chiplets will be used across a variety of market segments, from high-performance computing to IoT, 5G, automotive, medical imaging, edge computing, AI, and mobile devices. In all of these markets, chipmakers are under pressure to deliver higher performance and more domain-specific solutions, but at the same time many of these devices will be manufactured in much smaller volumes than smart phones or servers.

This is where a LEGO-like chiplet approach fits in, and UCIe is a central element in this strategy. In comparison to PCIe, UCIe’s shoreline bandwidth (linear) is 28 to 224 for a standard package, and 165 to 1317 GB/s/mm for an advanced package, an improvement of between 20 to more than 100. The latency for PCIe is approximately 20ns. At less than 2ns (Tx + Rx), UCIe provides a 10-fold improvement. The power efficiency is 0.5 (standard package) and 0.25 (advanced package) pJ/b, a more than 10-fold improvement. This is significant. Higher power efficiency translates into lower heat generation and ultimately higher reliability for semiconductors.

Three foundries — Intel, TSMC and Samsung — currently are working on 3nm process technology, and Intel’s roadmap extends below 2nm into the angstrom realm. But developing chips at those nodes requires significant challenges in yield learning and thermal dissipation, as well as new transistor types, new materials, as well as high-NA EUV lithography. By limiting what is developed at those advanced nodes, and packaging together other components such as accelerators and memory as separate chiplets, yield and time to market are both improved.

UCIe is an important development in that direction, and the first version addresses both 2D and 2.5D processes. A UCIe 3D process also is in the works, which is expected to further simplify chiplet connections and alleviate some of today’s manufacturing problems.

Fig. 1: UCIe will enable designers to separate functional blocks like processors, memories, controllers, RF, and I/O into chiplets in future semiconductor development. Source: UCIe Consortium

A typical SoC package includes multi-functional blocks such as processors, co-processors, accelerators, memories, and other controller and I/O functions. A chiplet approach separates these functional blocks into smaller chiplets. Instead of making a large monolithic die that includes all of these multi-functional blocks, UCIe provides a way for manufacturers to build processors and I/O chiplets separately and then connect these functional blocks (chiplets) later.

If any of the chiplets encounters problems in manufacturing, they can be discarded and replaced with other chiplets, but the rest of the components in that package will remain untouched. This approach boosts production efficiency, time to market, and saves costs. It also potentially offers more options as commercial chiplets are developed, allowing chipmakers to build exactly what a customer needs. These chiplets also can be re-used many times, such as in the case of memories, or they can be customized for a particular application.

For fabless designs today, a memory block can be re-used over and over again, but designers still have to go through the same design steps to integrate it into a monolithic chip or an advanced package. With a standardized interface, this process can be accelerated.

“For foundries, multi-die designs potentially mean more die tape-outs,” said Mick Posner, senior director product marketing at Synopsys. “The foundries also may try to facilitate multi-die business by offering some dies off-the-shelf that can be used similarly to how they are already employed for key IP blocks. This potentially will allow the foundries to better leverage capacity in ‘older’ nodes, even for very advanced designs.”

This is not a trivial effort, however. “For this to work, the die-to-die interfaces must be available across all the nodes in question,” Posner said. “Fabless chip designers will be able to focus on their differentiation factors and rely on die packaging for other ‘generic’ functions, much like they are doing with IP today. Potentially, chipmakers can expand their market by offering more scalable solutions and providing composable products in the form of chiplets for others to assemble with their secret sauce in a LEGO fashion (e.g., accelerators, GPUs, etc.). IP vendors could choose to expand the ecosystem by offering specialized IP subsystems in a hardened or known good die format with new business models based on license usage, royalties, and/or hardware volume basis.”

Others point to similar benefits. “The need for chiplet-based processors to improve performance and reduce cost is well understood,” said Jeff Defilippi, senior director of product management for Arm’s Infrastructure Line of Business. “But until recently, there has been little alignment on how to leverage the benefits of chiplet architectures beyond vendor-specific implementations. UCIe technology defines an open industry standard for establishing a ubiquitous interconnect at the package level, addressing customer requests for more customizable, package-level integration. It combines best-in-class die-to-die interconnect and protocols from an interoperable, multi-vendor ecosystem, and is architected and specified from the ground up to deliver the best KPIs while meeting wide adoption criteria. This enables end users to mix and match chiplet components from a multi-vendor ecosystem for SoC construction.”

Chiplets solve another thorny problem in chip design, as well. As more features are added into chips, including AI/ML, the physical size of chips continues to grow. But they are limited in manufacturing by the size of the reticle, which determines the amount of surface area on a wafer that can be exposed with a single mask without errors. Currently, the limit is between 800 and 850mm², a number set by what is possible with today’s lithography equipment. Within this limit, a designer can choose to produce many simple chips, or fewer complicated chips, such as those which combine processors, co-processors, memories, and I/O.

UCIe changes that formula, enabling chip designers to develop bespoke (custom) solutions for specific applications with less effort, shorter lead time, and better yield. For example, a communication chip that requires an RF modem, but which needs only two memory blocks, would be able to connect 3nm processors with 28nm RF, plus two memory blocks and other I/O. Using UCIe to connect these blocks gives designers a higher degree of flexibility.

Fig. 2: The costs of semiconductor development rise as die size becoming smaller. The UCIe manufacturing process will potentially slow down the rate of increase. Source: UCIe Consortium

Step one
UCIe 1.0 is the first open industry standard to support the die-to-die I/O physical layer, die-to-die protocols, and software stack based on the PCI Express (PCIe) and Compute Express Link (CXL) industry standards. It includes the industry’s leading KPIs, debug support, and compliance considerations. The goal is to ensure chipsets interconnect and interoperate. The future goals of UCIe include adding additional protocols defining advanced chiplet form-factors and management.

“UCIe is a comprehensive specification that aims to drive a coherent ecosystem around multi-die SoC designs,” said Shekhar Kapoor, senior director product marketing at Synopsys. “The UCIe Consortium has already released a die-to-die interface specification, which is more encompassing than the other options, covering the complete protocol stack as well as the physical layers. So it can address the most relevant multi-die SoC use cases. In contrast, other standard efforts have mostly focused on the physical layer aspects of the interface. In addition to completeness, the UCIe specification is compelling for the performance metrics it proposes, as measured by edge efficiency, power efficiency, and latency. UCIe also defines a coherent roadmap to align with expected future needs of the industry, including a focus on interoperability aspects via a well-defined set of definitions to avoid ambiguity.”

To put in perspective, Marvell, Intel, and AMD have been utilizing chiplet approaches for several generations of chips, giving them an inherent advantage over competitors. But as the rest of the industry begins adopting this LEGO-block approach it opens up similar customization capabilities for all chipmakers.

“Adoption of standardized definitions, together with the publication of standardized chiplet I/O interfaces that UCIe members commit to use in commercially available chiplets, should broaden and simplify adoption of chiplet technologies,” said Siemens’ Allan. “This could include reference kits, compliance documentation, and open support. The result would be that anyone wishing to use commercial chiplets can do so easily, just as designers today can use and integrate HBM memory into their designs. From a stability perspective, UCIe stands to benefit from the foundations of PCIe and CXL, which are rolling out to wide adoption in the market. This bodes well for the stability of a future UCIe solution. Also, security is expected to become a positive factor in chiplet adoption, because features that can be made more secure by placing them on-chip, might now be off-chip in a chiplet. The underlying PCIe/CXL protocols on which UCIe is based have a robust security implementation (IDE), which could play a part in providing security assurance for those who adopt chiplets.”

Fig. 3: Leaders in semiconductors, packaging, IP suppliers, foundries, and cloud service providers are joining together to drive a new open chiplet standard. Source: UCIe Consortium

Future development and challenges
Overall, the semiconductor industry is enthusiastic about the new standard. But this is just the starting point. The next step is to build an ecosystem of chiplets that are well characterized and proven in silicon.

“For chiplet-on-interposer designs, detailed physical implementation tools exist today, as do detailed post-layout extraction and signal integrity, power integrity, and thermal simulation tools,” said Ken Willis, product engineering architect for signal integrity at Cadence. “The key capability that still is needed is an enabling pre-design analysis environment for early feasibility and tradeoff analysis to help make architectural and system-level decisions on the implementation. This will require access to qualified chiplet analysis model libraries, representative interposer interconnect libraries, and the ability to rapidly ‘virtual prototype’ potential implementation approaches across interposer/package/board to enable multi-discipline analyses.”

Much more work lies ahead. “UCIe advocates have clearly defined their areas of focus, which include die-to-die I/O with industry leading KPIs, CXL/PCIe for near-term volume attach, and a well-defined specification that ensures interoperability and evolution,” said Keith Felton, product manager for the Embedded Board Systems division of Siemens EDA. “Looking ahead, UCIe should look to partner closely with other industry alliances focused on enabling commercialization and usage of chiplets such as the Chiplet Design Exchange (CDX) project that is part of the Open Compute Project’s ODSA/CDX Business working group.”

UCIe is an important first step. “There are a lot of different elements that go into a complete interface solution including protocol, PHY, security, management, debug, and form factor,” said Arm’s Defilippi. “The industry has been solving these issues in bespoke ways, and now UCIe will have the challenge of standardization of these elements.”

Still, with the backing of industry heavyweights, UCIe Specification 1.0 is gaining momentum. The emerging open-industry standard provides better performance, low power, and higher yield. In addition, the planned focus on 3-D is expected to promote the growth of the entire semiconductor ecosystem.

“Currently, the UCIe specification 1.0 addresses the 2D and 2.5D processes,” said Debendra Das Sharma, Intel senior fellow and chief architect for I/O technologies, and Standards Promoter Member of UCIe. “We expect to cover 3D in future releases. UCIe provides performance and power efficiency Improvement by defining the universal standard interface, and it will benefit the whole chiplets ecosystem. IP developer and chiplets manufacturers, including those making processors, memories, co-processors, accelerators, controllers, and the different types of I/O can now participate. Together they will accelerate future semiconductor innovations.”

Resources
Universal Chiplet Interconnect Express (UCIe): Building an Open Chiplet Ecosystem
Chiplets: Knowledge Center
Paving The Way To Chiplets
Chiplets: Current Status