tag: 10nm

Scaling The Lowly SRAM
By Mark LaPedus - 05 Jun, 2013 - Comments: 0

By Mark LaPedus Chipmakers face a multitude of challenges at the 20nm logic node and beyond, including the task of cramming more functions on the same chip without compromising on power and performance. There is one major challenge that is often overlooked in the equation—scaling the lowly static RAM (SRAM). In one key application, SRAM is the component used to make on-chip cache memories... » read more

GF’S Two Flavors Of FD-SOI
By Various Writers - 17 Apr, 2013 - Comments: 0

Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News ~  ~ Hearing the news that GlobalFoundries would be offering two flavors of FD-SOI, ASN asked the company to explain the strategy further. Here are the responses provided by Subi Kengeri, Vice President of Advanced Technology Architecture.   [caption id="" align="alignleft" width="110"] Subi Kengeri, VP Advanced T... » read more

Good Pattern Flow Ahead For 14, 10nm
By Ann Mutschler - 21 Feb, 2013 - Comments: 0

By Ann Steffora Mutschler Given complexity, yield, power and other challenges with leading edge manufacturing, semiconductor foundries increasingly have been forced to require more and more restrictive design rules with each new process node. “They keep adding more design rules and more operations to a particular check to eliminate corner cases where in manufacturing they saw some variant... » read more

Accelerating Moore’s Law
By Ed Sperling - 21 Feb, 2013 - Comments: 0

By Ed Sperling Ever since the inception of Moore’s Law, process nodes have moved forward at a rate of once every 18 to 24 months. Companies have been talking about slowing down the rate of progression as things get harder, but at least for the next couple of process nodes something very strange will occur—Moore’s Law will accelerate. The root cause is growing competition for a shrinki... » read more

Tech Talk: Getting To The Next Node
By Ed Sperling - 14 Feb, 2013 - Comments: 0

IBM's Gary Patton talks with Low-Power/High-Performance Engineering about finFETs, EUV, and the challenges of staying on the Moore's Law road map. [youtube vid=jtz9XSXyBp0] » read more

What Will Replace Dual Damascene?
By Mark LaPedus - 24 Jan, 2013 - Comments: 0

By Mark LaPedus In the mid-1990s, IBM announced the world’s first devices using a copper dual damascene process. At the time, the dual damascene manufacturing process was hailed as a major breakthrough. The new copper process enabled IC makers to scale the tiny interconnects in a device, as the previous material, aluminum, faced some major limitations. Dual damascene remains the workhorse... » read more

ST-Ericsson 28nm FD-SOI/ARM Chip Hits 2.8GHz at CES
By Various Writers - 22 Jan, 2013 - Comments: 0

Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News ~  ~ What a great start to 2013: at CES in Las Vegas, ST-Ericsson announced the NovaThor™ L8580 ModAp, “the world’s fastest and lowest-power integrated LTE smartphone platform.” This is the one that’s on STMicroelectronics’ 28nm FD-SOI, with sampling set for Q1 2013. And it’s a game changer – for users, fo... » read more

Challenges Grow For EUV
By Ed Sperling - 18 Oct, 2012 - Comments: 0

By Mark LaPedus In the late 1990s, a group led by Intel launched a consortium to propel extreme ultraviolet (EUV) lithography into the mainstream. Originally, the consortium, dubbed the EUV LLC, envisioned the advent of EUV scanners that would move into production at the 65nm node. Clearly, the now-defunct consortium underestimated the difficulties and challenges associated with EUV. ASM... » read more

Beam Me Up
By Ed Sperling - 18 Oct, 2012 - Comments: 0

By Mark LaPedus For years, electron-beam tools have been struggling to keep up with photomask complexity, causing an alarming increase in write times and mask production costs. Intel and others recently warned that e-beams soon could reach their fundamental limits, thereby requiring the need for new solutions. And in the multiple patterning era, mask makers could see their capital costs soa... » read more

Deep Inside Intel
By Ed Sperling - 18 Oct, 2012 - Comments: 0

By Ed Sperling Semiconductor Manufacturing & Design sat down with Mark Bohr, senior fellow at Intel, to talk about a wide range of manufacturing and design issues Intel is wrestling with at advanced nodes—and just how far the road map now extends. SMD: Will EUV make 10nm? And if it doesn’t, what effect will that have on Intel? Bohr: For a process module as critical as lithography... » read more

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