tag: 2.5D

New Apps For 3D Chips
By Ed Sperling - 15 Nov, 2012 - Comments: 0

By Mark LaPedus Semiconductor Manufacturing and; Design sat down to discuss the 3D device challenges and applications with Peter Ramm, head of the department for device and 3D integration at Fraunhofer EMFT Munich, one of Europe’s largest research organizations. SMD: Fraunhofer was a pioneer in 3D chip R&D, right? Ramm: We are the oldest microelectronics institute in Germany. We st... » read more

Experts At The Table: Stacked Die Reality Check
By Ed Sperling - 10 Sep, 2012 - Comments: 0

By Ed Sperling Semiconductor Manufacturing & Design sat down with Sunil Patel, principal member of the technical staff for package technology at GlobalFoundries; Steve Pateras, product marketing director at Mentor Graphics; Steve Smith, senior director of platform marketing at Synopsys; Thorsten Matthias, business development director at EVGroup; and Manish Ranjan, vice president of market... » read more

Experts at the Table: Stacking the Deck
By Ed Sperling - 23 Aug, 2012 - Comments: 0

By Ann Steffora Mutschler System-Level Design sat down to discuss challenges to 3D-IC adoption with Samta Bansal, product marketing for applied silicon realization in strategy and market development at Cadence; Carey Robertson, product marketing director at Mentor Graphics; Karthik Chandrasekar, member of technical staff in IC Design at Altera; and Herb Reiter, president of EDA2ASIC Consulting... » read more

Experts At The Table: Stacked Die Reality Check
By Ed Sperling - 16 Aug, 2012 - Comments: 0

By Ed Sperling Semiconductor Manufacturing & Design sat down with Sunil Patel, principal member of the technical staff for package technology at GlobalFoundries; Steve Pateras, product marketing director at Mentor Graphics; Steve Smith, senior director of platform marketing at Synopsys; Thorsten Matthias, business development director at EVGroup; and Manish Ranjan, vice president of market... » read more

The Changing Role Of The OSAT
By Ed Sperling - 31 Jul, 2012 - Comments: 0

By Ann Steffora Mutschler As process geometries and packaging technologies have matured over time, the OSAT (outsourced semiconductor assembly and test) provider has played an evolving role in the semiconductor packaging ecosystem. With true 3D chip stacking on the horizon, their role may evolve once again as ecosystem players jostle for position in the 3D universe. There are two things tha... » read more

Leveraging The Past
By Ed Sperling - 28 Jun, 2012 - Comments: 0

By Ann Steffora Mutschler It’s easy to forget that not every design today is targeted at 20nm, given the amount of focus put on the bleeding edge of technology. But in fact a large number of designs utilize the stability and reliability of older manufacturing nodes, as well as lower mask costs, by incorporating new design and verification techniques, with 2.5D designs being a prime example. ... » read more

Packaging Tradeoffs More Complex Than Ever
By Ed Sperling - 24 May, 2012 - Comments: 0

By Ann Steffora Mutschler Driven by high-speed interfaces, the demand for TSVs and the complexities that new process nodes bring, older packaging technologies like wirebonding can’t keep up. The latest and greatest flip chip technologies offer much more flexibility, but at a cost. As such, the package plays a larger role than ever in determining system specifications because, depending o... » read more

Managing Complexity With Advanced Packaging
By Ed Sperling - 22 Mar, 2012 - Comments: 0

By Ann Steffora Mutschler Engineering teams across the globe continue to pound the process geometry treadmill to stay on the curve of Dr. Moore to achieve better speed or lower power or smaller die—and it all adds up to increased complexity in the design and packaging. However, with advanced forms of die stacking such as package-on-package, silicon-in-package, 2.5D silicon interposer techno... » read more

Something Old, Something Borrowed
By Ed Sperling - 11 Nov, 2011 - Comments: 0

The basic rule of SoC design is that it needs to be created relatively quickly, work as planned, and that it can be manufactured at a reasonable cost and with good yield ramp. That eliminates revolutionary changes on the technology side, limits the number of new materials, and relegates the most dramatic shifts to the business. That’s why most of the most far-reaching technology research i... » read more

The 3D Power Factor
By Ed Sperling - 26 Aug, 2011 - Comments: 0

In the move to stacked die, one of the biggest issues is power. While chips using leading-edge processes already address this issue effectively through a variety of advanced techniques, the big question mark is what happens with the older technologies. The answer may not be quite so simple. While it’s still possible to use technology developed at older process nodes, it may not be exactly ... » read more

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