Hybrid Bonding Moves Into The Fast Lane


The industry’s unquenchable thirst for I/O density and faster connections between chips, particularly logic and cache memory, is transforming system designs to include 3D architectures, and hybrid bonding has become an essential component in that equation. Hybrid bonding involves die-to-wafer or wafer-to-wafer connection of copper pads that carry power and signals and the surrounding diele... » read more

What Future Processors Will Look Like


Mark Papermaster, CTO at AMD, sat down with Semiconductor Engineering to talk about architectural changes that are required as the benefits of scaling decrease, including chiplets, new standards for heterogeneous integration, and different types of memory. What follows are excerpts of that conversation. SE: What does a processor look like in five years? Is it a bunch of chips in a package? I... » read more

Software Infrastructure For Silicon Lifecycle Management


Semiconductor technology continues to deliver higher levels of logic density in the era of nanometer processes. System-on-chip (SoC) teams can deliver even higher functionality when coupled with the massive integration possibilities of three-dimensional integrated circuit (3DIC) architectures. However, this growth must be matched by increases in capabilities and productivity in the collection a... » read more

Electromagnetic Simulation And 3D-IC Interposers


By Matt Commens, Juliano Mologni, and Pete Gasperini Today’s 3D integrated circuit (3D-IC) technology is the culmination of 40 years of research in universities and laboratories scattered across the globe. Beginning with dynamic random-access memory (DRAM) deployments that appeared on the market a decade ago, 3D-IC has since expanded its reach. It is now decisively beginning to achieve the... » read more

Chipmaking In The Third Dimension


Every few months, new and improved electronics are introduced. They’re typically smaller, smarter, faster, have more bandwidth, are more power-efficient, etc. — all thanks to a new generation of advanced chips and processors. Our digital society has come to expect this steady drip of new devices as sure as the sun will rise tomorrow. Behind the scenes, however, engineers are working feve... » read more

Keeping IC Packages Cool


Placing multiple chips into a package side-by-side can alleviate thermal issues, but as companies dive further into die stacking and denser packaging to boost performance and reduce power, they are wrestling with a whole new set of heat-related issues. The shift to advanced packaging enables chipmakers to meet demands for increasing bandwidth, clock speeds, and power density for high perform... » read more

Center Stage: The Time For Hybrid Bonding Has Arrived


When the subject of hybrid bonding is brought up in the industry, the focus is often on how this technique is used to manufacture CMOS image sensors (CIS), an essential device for today’s digital cameras, particularly those found in smartphones. As such, CIS is a common touchpoint given the ubiquity of mobile phones, whether you hold a product from Apple, Samsung, or Huawei in your hands. ... » read more

Who Benefits From Chiplets, And When


Experts at the Table: Semiconductor Engineering sat down to discuss new packaging approaches and integration issues with Anirudh Devgan, president and CEO of Cadence; Joseph Sawicki, executive vice president of Siemens EDA; Niels Faché, vice president and general manager at Keysight; Simon Segars, advisor at Arm; and Aki Fujimura, chairman and CEO of D2S. This discussion was held in front of a... » read more

New End Markets, More Demand For Complex Chips


Experts at the Table: Semiconductor Engineering sat down to discuss economic conditions and how that affects chip design with Anirudh Devgan, president and CEO of Cadence; Joseph Sawicki, executive vice president of Siemens EDA; Niels Faché, vice president and general manager at Keysight; Simon Segars, advisor at Arm; and Aki Fujimura, chairman and CEO of D2S. This discussion was held in front... » read more

Artificial intelligence deep learning for 3D IC reliability prediction


New research from National Yang Ming Chiao Tung University, National Center for High-Performance Computing (Taiwan), Tunghai University, MA-Tek Inc, and UCLA. Abstract "Three-dimensional integrated circuit (3D IC) technologies have been receiving much attention recently due to the near-ending of Moore’s law of minimization in 2D IC. However, the reliability of 3D IC, which is greatly infl... » read more

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