tag: 3D

Manufacturing Bits: Oct. 22
By Mark LaPedus - 22 Oct, 2013 - Comments: 0

Natural lithography For years, researchers have been exploring the development of nanosphere lithography or natural lithography. Nanosphere lithography makes use of directed self-assembly (DSA) techniques. The process begins with self-assembly of a nanosphere mask onto a substrate. This is followed by deposition of a material through the mask. The University of Paderborn has put a new twis... » read more

Applied To Buy TEL
By Mark LaPedus - 24 Sep, 2013 - Comments: 0

In a deal that could shake-up the fab tool landscape, Applied Materials has announced a definitive agreement to acquire rival Tokyo Electron Ltd. (TEL) in a stock deal valued at around $9.3 billion. Under the terms of the blockbuster deal, Applied Materials will own approximately 68% of the new company and TEL will own about 32%.  The combined entities will have a new name, dual headquarter... » read more

Front End Comes To The Back End
By Jeff Chappell - 19 Sep, 2013 - Comments: 0

By Jeff Chappell For outsourced assembly and test (OSAT) houses either planning for or already offering through-silicon via (TSV) capability for their 3D packaging efforts, this has meant the front end is coming to the back end, in a manner of speaking. A bit of an exaggeration perhaps, as most generalizations are. But thanks to TSVs, in a very real sense some of what would typically be the... » read more

Manufacturing Bits: Aug. 27
By Mark LaPedus - 27 Aug, 2013 - Comments: 0

Growing tubes Single-wall carbon nanotubes could one day be used in electronics, optoelectronics, biomedical imaging and other applications. But the synthesis of nanotubes with defined chiralities has been a stumbling block. A chiral molecule is a molecule that has a non-superposable mirror image. The University of Southern California has shown that chirality-pure short nanotubes can be use... » read more

The Evolving Interconnect
By Ann Mutschler - 28 Mar, 2013 - Comments: 0

By Ann Steffora Mutschler Chip interconnect protocol requirements are evolving as designs move to 20nm and below process geometries, and not always in predictable ways. At least part of this is being driven by what an SoC is used for. The continued push to shrink features opens up real estate at each new process node. For the past decade, that real estate has been used to add more featu... » read more

More Than Data Management
By Ann Mutschler - 28 Mar, 2013 - Comments: 0

By Ann Steffora Mutschler Managing the people, the data and the technology are just as important as meeting the market window given that without these, the entire project wouldn’t function. Throw huge data set sizes, different cultures and business management issues into the mix and the challenges are many. Fortunately, these are issues that the semiconductor industry has been refining for ... » read more

What’s Before Stacked Die?
By Mark LaPedus - 13 Dec, 2012 - Comments: 0

By Mark LaPedus Advanced 2.5D/3D chip stacking has a number of challenges and is still a few years away from mass production. In fact, mass production may not occur until 2015 or 2016. But OEMs can ill afford to sit still and wait for 2.5D/3D technology to mature. So, until 2.5D/3D is ready for prime time, chipmakers and IC-packaging houses are under pressure to innovate and extend current ... » read more

Foundry Landscape Changes In 3D
By Mark LaPedus - 13 Dec, 2012 - Comments: 0

By Mark LaPedus Over the last year, leading-edge silicon foundries announced their new and respective strategies in the emerging 2.5D/3D chip arena. The ink is barely dry and now the foundry landscape is changing. One new vendor, Tezzaron Semiconductor, is entering the market. The 3D DRAM supplier plans to provide select 2.5D/3D foundry services within its recently acquired fab in Austin, T... » read more

Soitec’s Wafer Roadmap for Fully Depleted Planar and 3D/FinFET
By Various Writers - 24 May, 2012 - Comments: 0

The following is a special guest post by Steve Longoria, Senior VP of Worldwide Business Development at Soitec.  It first appeared as part of the Advanced Substrate News special edition on FD-SOI industrialization. ~~ Today’s semiconductor industry is moving through several challenging transitions that are creating a significant opportunity for Soitec to bring incremental value to th... » read more

Keeping Up With Complexity
By Ed Sperling - 31 Mar, 2011 - Comments: 0

By Ed Sperling There are two schools of thought in designing complex SoCs. One says that increasing complexity requires a higher level of abstraction. The other says providing enough detail to get the design right is the only effective way to do it. There are staunch proponents of both approaches, but what has been missing are bridges to tie the higher level of abstraction to the more labo... » read more

← Older posts Newer posts →

  • Sponsors

  • Standards/Organizations

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy