tag: EUV

Filtering Out Fab Problems
By Mark LaPedus - 20 Jul, 2017 - Comments: 1

Bertrand Loy, president and CEO of Entegris, sat down to discuss the semiconductor industry, process challenges and filter technology with Semiconductor Engineering. What follows are excerpts of that conversation. SE: What is the outlook for the IC industry? Loy: A lot of positive things are happening. Eighty percent of what we do are consumables, which would be chemistries and filters. ... » read more

The Week In Review: Manufacturing
By Mark LaPedus - 14 Jul, 2017 - Comments: 1

Market research SEMI has released its mid-year forecast at Semicon West. SEMI reported that worldwide sales of new semiconductor manufacturing equipment are projected to increase by 19.8% to a total of $49.4 billion in 2017, marking the first time that the semiconductor equipment market has exceeded the market high of $47.7 billion set in 2000. In 2018, 7.7% growth is expected, resulting in an... » read more

Manufacturing Bits: June 27
By Mark LaPedus - 27 Jun, 2017 - Comments: 0

World’s brightest laser The University of Nebraska-Lincoln has set the unofficial record for the world’s brightest laser. Researchers have focused a laser at a brightness of 1 billion times greater than the surface of the sun. This feat was accomplished using the so-called Diocles Laser at the University of Nebraska-Lincoln. The laser has a combination of peak power and a repetition ra... » read more

Inside Chip R&D
By Mark LaPedus - 15 Jun, 2017 - Comments: 1

Semiconductor Engineering sat down to discuss R&D challenges, EUV and other topics with Luc Van den hove, president and chief executive of Imec, an R&D organization in Belgium. What follows are excerpts of that conversation. SE: Clearly, Moore’s Law is slowing down. The traditional process cadence is extending from 2 years to roughly 2.5 to 3 years. Yet, R&D is not slowing down, right? ... » read more

New BEOL/MOL Breakthroughs?
By Mark LaPedus - 15 Jun, 2017 - Comments: 1

Chipmakers are moving ahead with transistor scaling at advanced nodes, but it's becoming more difficult. The industry is struggling to maintain the same timeline for contacts and interconnects, which represent a larger portion of the cost and unwanted resistance in chips at the most advanced nodes. A leading-edge chip consists of three parts—the transistor, contacts and interconnects. The ... » read more

2.5D, ASICs Extend to 7nm
By Mark LaPedus - 13 Jun, 2017 - Comments: 2

The leading-edge foundry market is heating up. For example, GlobalFoundries, Intel, Samsung and TSMC have recently announced their new and respective processes. The new processes from vendors range anywhere from 10nm to 4nm, although the current battle is taking place at 10nm and/or 7nm. In fact, one vendor, GlobalFoundries, this week will describe more details about its previously-announced... » read more

System Bits: June 6
By Ann Mutschler - 06 Jun, 2017 - Comments: 0

Silicon nanosheet-based builds 5nm transistor To enable the manufacturing of 5nm chips, IBM, GLOBALFOUNDRIES, Samsung, and equipment suppliers have developed what they say is an industry-first process to build 5nm silicon nanosheet transistors. This development comes less than two years since developing a 7nm test node chip with 20 billion transistors. Now, they’ve paved the way for 30 billi... » read more

Samsung Unveils Scaling, Packaging Roadmaps
By Ed Sperling - 24 May, 2017 - Comments: 5

Samsung Foundry unveiled an aggressive roadmap that scales down to 4nm, and which includes a fan-out wafer-level packaging technology that bridges chips in the redistribution layer, 18nm FD-SOI, and a new organizational structure that allows the unit much greater autonomy as a commercial enterprise. The moves put [getentity id="22865" e_name="Samsung Foundry"] in direct competition with [get... » read more

The Race To 10/7nm
By Mark LaPedus - 22 May, 2017 - Comments: 4

Amid the ongoing ramp of 16/14nm processes in the market, the industry is now gearing up for the next nodes. In fact, GlobalFoundries, Intel, Samsung and TSMC are racing each other to ship 10nm and/or 7nm technologies. The current iterations of 10nm and 7nm technologies are scaled versions of today’s 16nm/14nm finFETs with traditional copper interconnects, high-k/metal-gate and low-k diele... » read more

High-Stakes Litho Game
By Ed Sperling - 18 May, 2017 - Comments: 0

The commercial introduction of EUV looks all but assured these days. There is enough history to show it works. Uptime and throughput are improving, and systems are shipping today. The question now is how to measure its success. In the short-term, this is a fairly simple financial exercise for companies like ASML and Zeiss, which have been closely collaborating to get these massive systems ou... » read more

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