tag: IP

Experts At The Table: Who Takes Responsibility?
By Ed Sperling - 04 Oct, 2013 - Comments: 0

By Ed Sperling Semiconductor Engineering sat down with John Koeter, vice president of marketing and AEs for IP and systems at Synopsys; Mike Stellfox, technical leader of the verification solutions architecture team at Cadence; Laurent Moll, CTO at Arteris; Gino Skulick, vice president and general manager of the SDMS business unit at eSilicon; Mike Gianfagna, vice president of corporate market... » read more

IP-XACT Becoming More Useful
By Ed Sperling - 01 Oct, 2013 - Comments: 0

Accellera created analog/mixed signal extensions to the IEEE IP-XACT standard, and the standards group will recommend an update to the overall standard later this year to make it more useful for IP integration. IP-XACT has been considered a great idea since its introduction in 2009 because it allows IP makers to add metadata to their IP—information needed to integrate it into complex desig... » read more

Buying And Selling EDA Companies
By Ed Sperling - 26 Sep, 2013 - Comments: 0

By Ed Sperling Buying companies is the easy part. Integrating them is the hard part. It’s also the point where most acquisitions that go awry actually run into problems. There are widely different strategies for how to accomplish integration. Sometimes they work, other times they don’t. And sometimes both companies are surprised by the outcome—for better or worse. “Either you thi... » read more

Experts At The Table: Debug
By Ed Sperling - 26 Sep, 2013 - Comments: 0

By Ed Sperling Semiconductor Engineering sat down with Galen Blake, senior verification engineer at Altera; Warren Stapleton, senior fellow at Advanced Micro Devices; Stephen Bailey, director of solutions marketing at Mentor Graphics; Michael Sanie, senior director of verification marketing at Synopsys. What follows are excerpts of that conversation. SE: What are the big issues with debug? ... » read more

More Test Needed For Integrated IP
By Ann Mutschler - 26 Sep, 2013 - Comments: 0

By Ann Steffora Mutschler As the use and reuse of design IPs and cores has reached approximately 70% of the content of an SoC, the need for both pre- and post-silicon test has increased. On the pre-silicon side, test comes in the form of verification IP. Driving the addition of more strenuous test approaches on this side is a combination of forces that impact design, noted Tom Hackett, prod... » read more

New Risk Factors For SoCs
By Ed Sperling - 12 Sep, 2013 - Comments: 0

By Ed Sperling Third-party IP is becoming increasingly important in SoC designs. It saves development time and adds unique value. It also can improve performance and lower power, because a company specializing in IP frequently can build and optimize it better than a company that builds entire chips. But there are also plenty of landmines in IP integration, and there is a growing concern abo... » read more

Experts At The Table: Who Takes Responsibility?
By Ed Sperling - 12 Sep, 2013 - Comments: 0

By Ed Sperling Semiconductor Engineering sat down with John Koeter, vice president of marketing and AEs for IP and systems at Synopsys; Mike Stellfox, technical leader of the verification solutions architecture team at Cadence; Laurent Moll, CTO at Arteris; Gino Skulick, vice president and general manager of the SDMS business unit at eSilicon; Mike Gianfagna, vice president of corporate market... » read more

DDR White Paper
By Various Writers - 12 Sep, 2013 - Comments: 0

DDR DRAM memory controllers have many competing demands on them. A good memory controller must improve the bandwidth of the memory interface while respecting the latency demands of the CPU, graphics, and real-time DRAM in the system while maintaining compliance with memory bus and on-chip bus standards. The read reorder buffer (RRB) is a silicon-proven architectural enhancement available in... » read more

The Single Platform Strategy
By Kurt Shuler - 22 Aug, 2013 - Comments: 0

By Kurt Shuler For semiconductor companies in high-volume or emerging growth markets, the days of using multiple platforms to address different segments are over. The new era of using a single platform to address several different segments is rapidly taking hold. Adding fuel to this transition is the greater flexibility that design teams have to spin derivatives of those single platforms. T... » read more

Blog Review: Aug. 21
By Ed Sperling - 21 Aug, 2013 - Comments: 0

By Ed Sperling Mentor’s Michael Ford recalls the worst meetings in the world—ones that involve materials in the manufacturing process. Unfortunately there were a lot of them, so they were more like working in a recurring nightmare. Paging Freddie Krueger. Synopsys’ Karen Bartleson talks with Angisys CEO Anupam Bakshi about why EDA companies need to collaborate, and what’s the risk ... » read more

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