tag: IP

Experts At The Table: Low-Power Verification
By Ed Sperling - 16 Aug, 2013 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss power format changes with Sushma Hoonavera-Prasad, design engineer in Broadcom’s mobile platform group; John Biggs, consultant engineer for R&D and co-founder of ARM; Erich Marschner, product marketing manager at Mentor Graphics; Qi Wang, technical marketing group director at Cadence; and Jeffrey Lee, corporate ap... » read more

Why Does That App Make My Phone Hot?
By Adam Sherer - 08 Aug, 2013 - Comments: 0

By Adam Sherer Popular Mechanics examined this topic in 2011, focusing mostly on packaging and other physical conditions. “Poor signal, intense workload and battery charging” were quoted, but the verification engineer knows the part of that list that was glossed over—intense workload. The author of that article waved away that aspect, saying the operating system usually can handle the so... » read more

Mixing Custom And Standard Parts
By Ed Sperling - 08 Aug, 2013 - Comments: 0

By Ed Sperling The amount of third-party and re-used IP content in an SoC is on the rise, but once a decision to buy vs. make has been made it doesn’t always stay that way. In fact, chipmakers are swinging the pendulum back and forth across a variety of chips, building IP themselves, standardizing on another vendor’s IP, then sometimes rolling it back the other way. The reasons are usua... » read more

The Rise Of Semiconductor IP Subsystems
By Various Writers - 06 Aug, 2013 - Comments: 0

The semiconductor IP (SIP) market arose when SIP vendors created IP functions that mirrored those found in the discrete semiconductor market and made those functions available to SoC designers in the form of hard or soft SIP blocks. As the SoC and SIP markets evolved, it was a natural evolution that many discrete SIP functions be converged into larger blocks that mimic system-level functions (i... » read more

Experts At The Table: Performance Analysis
By Ed Sperling - 02 Aug, 2013 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down with Ravi Kalyanaraman, senior verification manager for the digital entertainment business unit at Marvell; William Orme, strategic marketing manager for ARM’s System IP and Processor Division; Steve Brown, product marketing and business development director for the systems and software group at Cadence; Johannes Stahl director o... » read more

3D IC Supply Chain: Still Under Construction
By Barbara Jorgensen - 25 Jul, 2013 - Comments: 1

By Barbara Jorgensen and Ed Sperling Stacked die, which promise high levels of integration, a tiny footprint, energy conservation and blinding speed, still have some big hurdles to overcome. Cost, packaging and manufacturability continue to make steady progress, with test chips being produced by all of the major foundries. But in a disaggregated ecosystem, the supply chain remains a big st... » read more

Raising The IP Abstraction Level
By Ed Sperling - 25 Jul, 2013 - Comments: 0

By Ed Sperling An increasing reliance on commercial and re-used IP and more emphasis placed on software development is adding even more pressure onto semiconductor design teams to figure out the benefits and limitations of myriad possible choices earlier in the design process. Design teams already are under pressure to meet increasingly tighter market deadlines, and it is stressing every pa... » read more

System-Level Security Issues
By Ed Sperling - 25 Jul, 2013 - Comments: 0

The more things that are put onto a single SoC, the greater the possibility that the entire system can be hacked. Centralization is good from the standpoint of speed, cost and power, but it’s not always good from the standpoint of security. This may sound contrary to the experience of corporate IT departments, but there’s a reason behind this. In the case of data centers, the advent of t... » read more

The Week In Review: July 19
By Ed Sperling - 19 Jul, 2013 - Comments: 0

By Ed Sperling Synopsys rolled out a 28nm data converter IP portfolio for analog-to-digital and digital-to-analog converters, as well as integrated PLLs. Synopsys says the new architecture saves up to 76% of the power and 86% of area. Mentor Graphics added intelligent software-driven verification to its functional verification platform. New is the ability to automatically generate embedded ... » read more

Changes And Challenges
By Ed Sperling - 18 Jul, 2013 - Comments: 0

At 130nm, the shift to copper interconnects and 300mm wafer sizes was considered to be the most difficult transition in its long and incredibly efficient history. The next chapter will be even tougher. It’s not that change is a foreign concept to semiconductor design and manufacturing. In fact, it’s probably the only constant over the past 50 years. But in the past, those changes tended ... » read more

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