tag: Mentor Graphics

Defining The Edge Of IoT
By Jeff Miller - 02 Mar, 2017 - Comments: 0

“Life on the edge of IoT is where creativity knows no bounds.” Brian Derrick, Vice President Corporate Marketing and General Manager, Mentor Graphics. We are living in a remarkable time for electronic product design and development. In his blog post, Brian Derrick explores how the race to create the latest smartphones results in the availability of advanced, low-cost sensors, which has... » read more

Blog Review: March 1
By Jesse Allen - 01 Mar, 2017 - Comments: 0

In a video, Mentor's Wally Rhines discusses the evolution of test methodologies and the forces that will change test priorities. Cadence's Priya Balasubramanian explores memory trends in data servers driven by the Internet's massive need for bandwidth. Synopsys' Aadil Trikha presents a primer on the types of AMBA ACE barrier transactions. ARM's Simon Segars examines the state of IoT de... » read more

What Does An AI Chip Look Like?
By Ed Sperling - 01 Mar, 2017 - Comments: 5

Depending upon your point of reference, artificial intelligence will be the next big thing or it will play a major role in all of the next big things. This explains the frenzy of activity in this sector over the past 18 months. Big companies are paying billions of dollars to acquire startup companies, and even more for R&D. In addition, governments around the globe are pouring additional... » read more

The Week In Review: Design
By Jesse Allen - 24 Feb, 2017 - Comments: 0

M&A ARM made two acquisitions to add the new NarrowBand-IoT (NB-IoT) low power wide area connectivity standard to its designs: Mistbase, founded in 2015 in Sweden, provides a complete NB-IoT physical layer implementation solution, while London-based NextG-Com, founded in 2008, offers a complete layer two and three software stack for NB-IoT. Tools Synopsys released the latest versio... » read more

Could DVCon Be Better?
By Brian Bailey - 23 Feb, 2017 - Comments: 0

DVCon is undoubtedly the best conference in the industry if your interest is functional verification. In the past, it has also had a slant toward design. The focus is quite simply based on the standards activity going on within [getentity id="22028" e_name="Accellera"], the EDA industry's body that turns problems into solution in a short space of time. As those standards mature, they are handed... » read more

IP Qualification During RTL Synthesis
By Sudhakar Jilla - 23 Feb, 2017 - Comments: 0

By Sudhakar Jilla and Arvind Narayanan The use of IP (intellectual property) as basic building blocks is an established practice for SoC designs. Most IP is developed without chip-level context and very little knowledge about physical design, which can introduce unwanted schedule risk into the design process. Much of the risk of IP development can be mitigated by using new physical synthesis... » read more

Custom Hardware Thriving
By Ann Mutschler - 23 Feb, 2017 - Comments: 0

In the early days of the IoT, predictions about the commoditization of hardware and the end of customized hardware were everywhere. Several years later, those predictions are being proven wrong. Off-the-shelf components have not replaced customized hardware, and software has not dictated all designs. In fact, in many cases the exact opposite has happened. And where software does play an elev... » read more

Fault Simulation Reborn
By Brian Bailey - 23 Feb, 2017 - Comments: 0

Fault simulation, one of the oldest tools in the EDA industry toolbox, is receiving a serious facelift after it almost faded from existence. In the early days, fault simulation was used to grade the quality of manufacturing test vectors. That task was replaced almost entirely by [getkc id="173" comment="scan test"] and automatic test pattern generation (ATPG). Today, functional safety is cau... » read more

IP Qualification with Oasys-RTL
By Mentor, a Siemens Business - 22 Feb, 2017 - Comments: 0

With increasing design sizes and complexities, the use of IP (intellectual property) as basic building blocks for better SoC design is also increasing. This paper presents the challenges faced during IP integration at the SoC level and what can be done to mitigate those risks during IP development. Mentor’s Oasys-RTL RTL floorplanning and physical synthesis tool offers a unique IP qualificati... » read more

Blog Review: Feb. 22
By Jesse Allen - 22 Feb, 2017 - Comments: 0

Mentor's Brian Derrick digs into the state of the electric vehicle industry and whether established OEMs will be able to make the changes required to meet new consumer demands. Cadence's Paul McLellan listens in on how to greatly improve the efficiency of machine learning, without using custom hardware, in a talk by Stanford's Kunle Olukotun. Synopsys' Robert Vamosi warns not to overlook ... » read more

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