tag: SIP

Taking Advantage Of Outsourced Test Services
By Vineet Pancholi - 19 Nov, 2020 - Comments: 0

The business model in today’s competitive world of commerce has shifted over recent years to “services.” Companies like Microsoft, Amazon and Google are prime success stories that have advanced the industry with business-enabling services. These economic productivity improvement services allow their customers to focus on product architecture, design and quick time to market. The service p... » read more

Packaging Demands For RF And Microwave
By Ken Molitor - 22 Oct, 2020 - Comments: 0

RF and microwave integrated circuits (ICs), monolithic microwave ICs (MMICs) and systems in package (SiPs) are vital for a wide range of applications. These include mobile phones, wireless local-area networks (WLANs), ultra-wideband (UWB), internet-of-things (IoT), GPS and Bluetooth devices. Moreover, RF-optimized packaging products and processes are essential to enabling the 5G ramp-up. RFI... » read more

Protecting Chiplet Architectures With Hardware Security
By Scott Best - 08 Oct, 2020 - Comments: 0

Chiplets are gaining significant traction as they provide compelling benefits for advancing semiconductor performance, costs, and time to market. With Moore’s Law slowing, building more powerful chips translates into building bigger chips. But with chip dimensions pushing up against reticle limits, growing the size of chips is increasingly impractical. Chiplets offer a new path forward by dis... » read more

What Worked, What Didn’t In 2019
By Brian Bailey - 19 Dec, 2019 - Comments: 1

2019 has been a tough year for semiconductor companies from a revenue standpoint, especially for memory companies. On the other hand, the EDA industry has seen another robust growth year. A significant portion of this disparity can be attributed to the number of emerging technology areas for semiconductors, none of which has reached volume production yet. Some markets continue to struggle, a... » read more

System-in-Package For Heterogeneous Designs
By Paul McLellan - 12 Dec, 2019 - Comments: 1

System integration is increasingly being done using 3D packaging technologies rather than integrating everything onto a huge SoC. One motivation is the ability to not just to split up a design in a single process, but to package die from different processes. Sometimes there are economic reasons. Several presentations at HOT CHIPS had a partition of the design into the processor itself, and a... » read more

Is There A Crossover Point For Mainstream Anymore?
By Ed Sperling - 21 Nov, 2019 - Comments: 0

Until 28nm, it was generally assumed that process nodes would go mainstream one or two generations after they were introduced. So by the time the leading edge chips for smartphones and servers were being developed at 16/14nm and 10/7nm, it was assumed that developing a chip at 28nm would be less expensive, less complex, and that the process rule deck would shrink. That worked for decades. Th... » read more

Automation And Correct By Construction Will Empower 3D-IC Adoption
By Youngsoo Lee - 27 Jun, 2019 - Comments: 0

When research on 3D ICs was in full swing around 2009, I had been researching on how through-silicon-via (TSV) was related to thermal in a semiconductor chip-making company, and it seemed logical that 3D ICs would become mainstream. However, during the past 10 years, use of 3D stacked die has been applied to only a few applications, such as memory or image sensors, and the 2.5D solution using i... » read more

Sidestepping Moore’s Law
By Mark LaPedus - 20 Jun, 2019 - Comments: 2

Calvin Cheung, vice president of engineering at ASE, sat down with Semiconductor Engineering to talk about advanced packaging, the challenges involved with the technology, and the implications for Moore’s Law. What follows are excerpts of that conversation. SE: What are some of the big issues with IC packaging today? Cheung: Moore’s Law is slowing down, but transistor scaling will co... » read more

Moore’s Law Now Requires Advanced Packaging
By Ed Sperling - 18 Apr, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss advanced packaging with Calvin Cheung, vice president of engineering at ASE; Walter Ng, vice president of business management at UMC; Ajay Lalwani, vice president of global manufacturing operations at eSilicon; Vic Kulkarni, vice president and chief strategist in the office of the CTO at ANSYS; and Tien Shiah, senior manager for memory at Samsung. W... » read more

Speedchip FPGA Chiplets
By Achronix - 09 Jan, 2019 - Comments: 0

Next-generation SoC platforms are evolving rapidly to process and move enormous amounts of data from the edge; over the network and to the cloud for high data and compute intensive applications such as AI and machine learning, high-performance computing (HPC) and autonomous driving. As a result, next-generation ASICs need to be larger, faster and further optimized for performance, power and are... » read more

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