tag: Synopsys

Blog Review: Nov. 3
By Jesse Allen - 03 Nov, 2021 - Comments: 0

In a blog for Arm, Matthew Griffin of the 311 Institute warns that cybersecurity is an increasingly pressing problem, with large criminal organizations raking in large sums of money and attacks able to impact a wide range of physical systems. Cadence's Paul McLellan checks out Google's video encoder chip and how it helps lower the CPU recycles required by the vast number of videos uploaded t... » read more

Week In Review: Design, Low Power
By Jesse Allen - 29 Oct, 2021 - Comments: 0

Arteris IP uncorked its initial public offering this week, a rare occurrence for a semiconductor IP vendor over the past couple decades. The stock began trading on the Nasdaq Global Market on Wednesday under the ticker symbol AIP, gaining more than 40% on its first day. Tools Codasip updated its Studio processor design toolset. Version 9.1 includes an expanded bus support with full AXI for ... » read more

What’s Next For Emulation
By Brian Bailey - 28 Oct, 2021 - Comments: 1

Emulation is now the cornerstone of verification for advanced chip designs, but how emulation will evolve to meet future demands involving increasingly dense, complex, and heterogeneous architectures isn't entirely clear. EDA companies have been investing heavily in emulation, increasing capacity, boosting performance, and adding new capabilities. Now the big question is how else they can le... » read more

Partitioning For Better Performance And Power
By Ann Mutschler - 28 Oct, 2021 - Comments: 0

Partitioning is becoming more critical and much more complex as design teams balance different ways to optimize performance and power, shifting their focus from a single chip to a package or system involving multiple chips with very specific tasks. Approaches to design partitioning have changed over the years, most recently because processor clock speeds have hit a wall while the amount of d... » read more

High-Level Synthesis For RISC-V
By Brian Bailey - 28 Oct, 2021 - Comments: 2

High-quality RISC-V implementations are becoming more numerous, but it is the extensibility of the architecture that is driving a lot of design activity. The challenge is designing and implementing custom processors without having to re-implement them every time at the register transfer level (RTL). There are two types of high-level synthesis (HLS) that need to be considered. The first is ge... » read more

Intelligent Coverage Optimization: Verification Closure In Hyperdrive
By Anika Malhotra - 28 Oct, 2021 - Comments: 0

Coverage dominates every aspect of verification for today’s complex IP and chip designs. Coverage metrics provide critical feedback on what has been verified and what has not, especially when automated stimulus generation techniques are used. All modern hardware design and verification languages include constructs for functional coverage specification and support a range of structural coverag... » read more

Co-Packaged Optics And The Evolution Of Switch/Optical Interconnects In Data Centers
By Synopsys - 27 Oct, 2021 - Comments: 0

Driven by a need to reduce power and increase bandwidth density in data center network switches and other devices, the data networking industry is moving toward adoption of co-packaged optics (CPO). This paper provides a brief overview of the history of copper and optical interconnects, the limitations of existing interconnect solutions, and the future of co-packaged optics, including the benef... » read more

Blog Review: Oct. 27
By Jesse Allen - 27 Oct, 2021 - Comments: 0

Siemens EDA's Ray Salemi continues looking into using Python for verification by looking at how pyuvm simplifies and refactors the UVM TLM system to take advantage of the fact that Python has multiple inheritance and no typing. Cadence's Paul McLellan listens in as Larry Disenhof explains the impact that export regulations have on EDA tools and IP products and changes in a rapidly shifting l... » read more

Week In Review: Auto, Security, Pervasive Computing
By Ed Sperling - 22 Oct, 2021 - Comments: 0

An investigation by the Automobile Association of America found that lane-keeping assist and automatic emergency braking, both high-profile ADAS features, are prone to failure in rain. According to the report, 69% of tests conducted with simulated rainfall resulted in test vehicles crossing lane markers, and 33% of simulations resulted in collisions at 35 mph. Surprisingly, risk of accidents di... » read more

Week In Review: Design, Low Power
By Jesse Allen - 22 Oct, 2021 - Comments: 0

Tools Cadence's digital and custom/analog flows were certified for TSMC's N3 and N4 process technologies. Updates for the digital flow includes efficient processing of large libraries, additional accuracy during library cell characterization and static timing analysis, and support for accurate leakage calculation required in N3 and static power calculation for new N3 cells. Synopsys' digita... » read more

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