tag: Synopsys

Challenges For New AI Processor Architectures
By Brian Bailey - 29 Jul, 2021 - Comments: 0

Investment money is flooding into the development of new AI processors for the data center, but the problems here are unique, the results are unpredictable, and the competition has deep pockets and very sticky products. The biggest issue may be insufficient data about the end market. When designing a new AI processor, every design team has to answer one fundamental question — how much flex... » read more

Sweeping Changes Ahead For Systems Design
By Ann Mutschler - 29 Jul, 2021 - Comments: 0

Data centers are undergoing a fundamental change, shifting from standard processing models to more data-centric approaches based upon customized hardware, less movement of data, and more pooling of resources. Driven by a flood of web searches, Bitcoin mining, video streaming, data centers are in a race to provide the most efficient and fastest processing possible. But because there are so ma... » read more

Optimize Physical Verification Cost Of Ownership
By Manoz Palaparthi - 29 Jul, 2021 - Comments: 0

As semiconductor designs continue to grow in size and complexity, they put increasing pressure on every stage of the design process. Physical verification, often on the critical path to tape-out, is especially affected. Design rule checking (DRC), layout versus schematic (LVS), and other physical verification runs take longer as chip size increases. In addition, finer geometries introduce new c... » read more

Continuous Education For Engineers
By Brian Bailey - 29 Jul, 2021 - Comments: 0

Continuous education is essential for engineers, but many companies don't recognize the value or they are unwilling to provide the necessary resources. This should be a line of questioning before every new hire makes the decision about where they want to work, because it not only affects their future career, but also impacts the value they can provide to that company during the course of the... » read more

Parallel RTL Exploration With Unparalleled Accuracy
By Synopsys - 28 Jul, 2021 - Comments: 0

Increasing chip complexity and restrictive advanced node rules have made it harder for implementation tools to achieve PPA targets and node entitlements via last-mile optimizations. RTL Architect enables designers to "shift-left" and predict the implementation impact of their RTL. RTL designers, SoC integrators, and IP developers have embraced this fast, predictive technology to give them new i... » read more

Blog Review: July 28
By Jesse Allen - 28 Jul, 2021 - Comments: 0

Synopsys' Chris Clark considers potential vulnerabilities in automotive over-the-air updates and best practices and new standards the industry can implement to improve security of vehicle software updates. Cadence's Paul McLellan gets a look at expected new fab construction in the coming years and where capacity is being focused. Siemens' Robin Bornoff dives into electromagnetic simulatio... » read more

Week In Review: Design, Low Power
By Jesse Allen - 23 Jul, 2021 - Comments: 0

Tools Cadence unveiled Cerebrus Intelligent Chip Explorer, a new machine learning-based tool to drive the Cadence RTL-to-signoff implementation flow. The tool aims to use reinforcement learning to find flow solutions that otherwise might not be explored and applies models to future designs. The company says it can improve productivity up to 10X and PPA up to 20% with optimization of the flow f... » read more

Week In Review: Auto, Security, Pervasive Computing
By SE Staff - 23 Jul, 2021 - Comments: 0

Security Xilinx is investing an undisclosed amount in fabless semiconductor startup Kameleon Security, which is working on a cyber protection chip for servers, data centers, and cloud computing. The proactive Security Processing Unit (ProSPU) already secures the boot and has a root of trust (RoT). The chip will be demonstrated at the Open Compute Project (OCP) Global Summit, which is planned f... » read more

Blog Review: July 21
By Jesse Allen - 21 Jul, 2021 - Comments: 0

Cadence's Paul McLellan listens in as Partha Ranganathan of Google argues that a new era of Moore's Law is emerging, defined both by the efficient design of hardware accelerators and improving the ways that hardware is utilized. Siemens EDA's Chris Spear continues exploring classes in SystemVerilog with a look at the relationship between the class variables that point to an object and how to... » read more

New Power, Performance Options At The Edge
By Heidi Elliott - 21 Jul, 2021 - Comments: 0

Increasing compute intelligence at the edge is forcing chip architects to rethink how computing gets partitioned and prioritized, and what kinds of processing elements and memory configurations work best for a particular application. Sending raw data to the cloud for processing is both time- and resource-intensive, and it's often unnecessary because most of the data collected by a growing nu... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy