Chip Industry Week in Review


Government funding/defunding NIST is terminating funding for the SMART USA Institute, a CHIPS Act research center focused on digital twins, prompting congressional concern that the decision disrupts active awards and weakens U.S. semiconductor R&D commitments. Korea Zinc was awarded $210M in CHIPS Act funding towards a new $6.6B Tennessee advanced smelter and minerals processing facility,... » read more

Faster Mask Synthesis With GPUs


Design teams face rising pressure to deliver larger chips with higher transistor densities on tighter schedules using advanced node processing. The computing demands of modern applications, especially those making heavy use of AI, are extending pressure beyond design to every step of the development flow, including manufacturing, where photolithography and mask synthesis must keep pace. This po... » read more

Reliability Risks Shift To The Materials Stack


The semiconductor industry’s push into 3D integration and large-format substrates has fundamentally changed the role of materials in packaging. What were once structural supports and electrical insulators have become critical performance limiters. Modern packages contain far more polymers, adhesives, advanced dielectrics, thermal materials, and composite laminates than previous generations... » read more

Benefits And Limits Of Using ML For Materials Discovery


Machine learning tools can accelerate all stages of materials discovery, from initial screening to process development. Whether the goal is to identify new applications for known materials or to design new molecules for a particular task, these tools help materials scientists find correlations in large data libraries. Still, machine learning tools are not magic. “Software tools are only as... » read more

Scalable End-To-End Test Solutions For Today’s Complex SoCs


By Srikanth Venkat Raman and Sri Ganta Today’s highly complex and large system on chip (SoC) devices and systems present many challenges to be addressed from manufacturing tests to the field while meeting stringent requirements for test costs, test quality, yield, debug, and turn-around-times. Scalable and efficient end-to-end test solutions that scale to large and complex SoC design cores... » read more

AI Workloads at the Edge: Ensuring Performance, Privacy, and Security


Experts At The Table: Semiconductor Engineering gathered a group of experts to discuss why some AI workloads are better suited for on-device processing to achieve consistent performance, avoid network connectivity issues, reduce cloud computing costs, and ensure privacy. The panel included Frank Ferro, group director in the Silicon Solutions Group at Cadence; Eduardo Montanez, vice president a... » read more

Blog Review: Dec. 17


Cadence's Shyam Sharma checks out what's new in the latest Open NAND Flash Interface 5.2 standard, including a Separate Command Address protocol that allows Hosts to optimize the command and data scheduling to increase overall available bandwidth. Siemens' Kyle Fraunfelter and Melville Bryant contend that improving semiconductor manufacturing and fab sustainability starts with a digital twin... » read more

Chip Industry Week in Review


Deals of the week: Arteris announced plans to acquire cybersecurity provider Cycuity. “Expanding our technology portfolio to include Cycuity’s hardware security assurance products will enable our customers to achieve secure on-chip data movement,” said Charlie Janac, chairman and CEO of Arteris. Qualcomm acquired Ventana Micro Systems, a maker of RISC-V data center-class CPU IP. ... » read more

PCIe 8.0: Preparing For The Next Doubling


By Monica Olvera and Gustavo Pimentel Every few years, the industry confronts the same challenge: can general-purpose I/O double again without overwhelming power budgets, overwhelming signal-integrity limits, or fragmenting the ecosystem? With PCIe 8.0, the answer appears to be yes—if the entire stack continues to advance together. Public PCI-SIG information outlines an objective of 256.0 ... » read more

AI Buildout Makes HPC Simulation More Challenging


Simulations of semiconductors and systems are becoming bigger, more complex, and increasingly necessary, mirroring everything that is happening to the hardware itself — particularly in AI data centers. The move beyond monolithic chips to multi-die assemblies now requires solving some thorny multi-physics challenges, such as thermal and power delivery, which are increasingly difficult to mo... » read more

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