tag: Synopsys

Data Overload In The Data Center
By Ed Sperling - 25 Jan, 2021 - Comments: 0

Dealing with increasing volumes of data inside of data centers requires an understanding of architectures, the flow of data between memory and processors, bandwidth, cache coherency and new memory types and interfaces. Gary Ruggles, senior product marketing manager at Synopsys, talks about how these systems are being revamped to improve performance and reduce power. » read more

Customer-Developed, Hyper-Convergent Design Flows Are Now Possible
By John Faase - 25 Jan, 2021 - Comments: 0

We all know the days of sequential, compartmentalized chip design are over. In advanced technology nodes, placement impacts performance, performance impacts power, and routing impacts everything. The way to manage these challenges is to interleave design tasks. For example, provide information on late-stage routing to early-stage synthesis tools to improve convergence. This technique is commonl... » read more

Week In Review: Design, Low Power
By Jesse Allen - 22 Jan, 2021 - Comments: 0

Cadence will acquire NUMECA International, a provider of computational fluid dynamics (CFD), mesh generation, multi-physics simulation, and optimization solutions for industries including aerospace, automotive, industrial, and marine. “Next-generation products and systems require comprehensive multi-physics engineering solutions encompassing IP, semiconductors, IC packaging, modules, board... » read more

Blog Review: Jan. 20
By Jesse Allen - 20 Jan, 2021 - Comments: 0

Siemens EDA's Harry Foster takes a look at the amount of time IC and ASIC projects spend in verification, changes in the number of engineers on a project, and how engineers are spending their time. Synopsys' Stelios Diamantidis considers the importance of specialized accelerators for AI workloads as both cloud and edge push the PPA limits of current technologies. Cadence's Paul McLellan p... » read more

Hidden Costs In Faster, Low-Power AI Systems
By Ed Sperling - 20 Jan, 2021 - Comments: 1

Chipmakers are building orders of magnitude better performance and energy efficiency into smart devices, but to achieve those goals they also are making tradeoffs that will have far-reaching, long-lasting, and in some cases unknown impacts. Much of this activity is a direct result of pushing intelligence out to the edge, where it is needed to process, sort, and manage massive increases in da... » read more

Von Neumann Is Struggling
By Brian Bailey - 18 Jan, 2021 - Comments: 5

In an era dominated by machine learning, the von Neumann architecture is struggling to stay relevant. The world has changed from being control-centric to one that is data-centric, pushing processor architectures to evolve. Venture money is flooding into domain-specific architectures (DSA), but traditional processors also are evolving. For many markets, they continue to provide an effective s... » read more

Week In Review: Design, Low Power
By Jesse Allen - 15 Jan, 2021 - Comments: 0

Qualcomm will acquire data center chip startup Nuvia for approximately $1.4 billion. Nuvia is working on a data center SoC and Arm-based CPU core it claims will lower performance per total cost of ownership by matching high performance with high efficiency and limiting maximum power to that which can be dissipated in an air-cooled environment. Qualcomm said Nuvia's technology would be incorpora... » read more

Die-To-Die Stress Becomes A Major Issue
By Ann Mutschler - 14 Jan, 2021 - Comments: 2

Stress is becoming more critical to identify and plan for at advanced nodes and in advanced packages, where a simple mismatch can impact performance, power, and the reliability of a device throughout its projected lifetime. In the past, the chip, package, and board in a system generally were designed separately and connected through interfaces from the die to the package, and from the packag... » read more

More Data, More Memory-Scaling Problems
By Bryon Moyer - 14 Jan, 2021 - Comments: 0

Memories of all types are facing pressures as demands grow for greater capacity, lower cost, faster speeds, and lower power to handle the onslaught of new data being generated daily. Whether it's well-established memory types or novel approaches, continued work is required to keep scaling moving forward as our need for memory grows at an accelerating pace. “Data is the new economy of this ... » read more

112G SerDes Modeling And Integration Considerations
By Priyank Shukla - 14 Jan, 2021 - Comments: 0

The ever-increasing demand for compute power and data processing in accelerators, intelligence processing units (IPUs), GPUs, as well as training and inference SoCs is driving the adoption of 112G SerDes PHY IP solutions. Ensuring a reliable Ethernet link and efficient integration are the most essential requirements that designers need to meet. IBIS-AMI modeling can help predict SerDes link per... » read more

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