Blog Review: Nov. 5


Synopsys' Igor Markov points out how numerical simulation tools advance quantum computing R&D by capturing both quantum-mechanical behavior and classical electromagnetic effects so researchers can evaluate design alternatives before fabrication and gain insight into how devices operate under realistic conditions. Siemens' Stephen V. Chavez finds that impedance modeling and control are mi... » read more

The Next Big Thing


Sometimes, we spend so much time looking for the next big thing that we actually miss something even bigger. I have to admit I was guilty of this while employed by a large EDA company 20 years ago. I was one of those ESL people — Electronic System Level acolytes, with Gary Smith as our standard bearer. We wanted to do many things, including raising the level of abstraction for design and veri... » read more

Chip Industry Week in Review


San Francisco-based Substrate raised more than $100 million to build a vertically integrated foundry that uses particle accelerators to produce "the world's brightest beams, enabling a new method of advanced X-ray lithography." The company claims its technology is comparable to ASML's high NA EUV, and notes it can extend well beyond 2nm. ASML has not publicly commented. The Nexperia chip sho... » read more

Top Five Trends In RTL Signoff


By Suresh Babu Barla and Rimpy Chugh The “shift left” of the development cycle is critical for the huge, complex chips used in such applications as AI and high-performance computing (HPC). Identifying design issues at the netlist stage occurs far too late in the design development process. At this point, addressing such problems demands significant effort, primarily because most design-r... » read more

Thermal, Mechanical, And Material Stresses Grow With Die Stacking


Managing thermal and mechanical stress in multi-die assemblies will require a detailed knowledge of how and where a device will be used, how it will be packaged, and where stresses could cause problems at any point during its expected lifetime. This includes everything from workload-dependent thermal gradients to mechanical and electrical stress, which may become more pronounced over time wi... » read more

Even With AI Inroads, Human Chip Designers Still Essential


The proliferation of AI tools seems perfectly matched to fill a talent shortage, but a closer look shows the skills do not entirely overlap. Certain parts of the EDA pipeline require human engineers, and it seems likely to stay that way for the foreseeable future. The dark art of analog design, the final word on safety-critical functional safety, high-level architectural decisions, product i... » read more

Advances In Formal Verification Technology


Experts at the table: Semiconductor Engineering sat down to discuss advances in formal verification tools and methodologies with Ashish Darbari, CEO for Axiomise; Jin Zhang, product management group director for the Verification Group at Cadence; Sean Safarpour, executive director for R&D at Synopsys; and Jeremy Levitt, principal engineer for Digital Verification Technology at Siemens EDA.... » read more

Blog Review: Oct. 29


Siemens' Ujjwal Negi and Prashant Dixit warn that while UCIe 3.0 improves performance and efficiency through higher data rates, runtime recalibration, priority sideband messaging, low-power sideband operation, and circular buffer transport, those enhancements also increase verification complexity. Cadence's Anika Sunda suggests that a unified digital thread that connects verification environ... » read more

Ensuring Reliability Becomes Harder In Multi-Die Assemblies


Multi-die assemblies are bringing together a variety of materials and processes with distinctly different physical properties, creating significant challenges in manufacturing and packaging that can impact yield at time zero and reliability in the field. What passes electrical screening at the end of the line may look good on paper, but these devices can still fail once exposed to rapid and ... » read more

Charting The Frontiers Of Photomask Technology And Extreme Ultraviolet Lithography


The enormous computing demands of AI and high-performance computing (HPC) applications are putting intense pressure on every aspect of chip development. Challenges arise during architecture, design, and verification, persist through the manufacturing process, and extend to post-silicon lifecycle management as chips are deployed in the field. Lithography, the fabrication step of shining light... » read more

← Older posts Newer posts →