FPGAs Find New Workloads In The High-Speed AI Era


FPGAs are finding new applications in the age of artificial intelligence, high-speed wireless communications, medical and life science technology, and in complex chip architectures where they can improve the flow of data. Field-programmable gate arrays (FPGAs) enable designers to reprogram or reconfigure digital logic after the chips have been deployed, which is essential in the AI world, wher... » read more

The Real-World Impact Of Silicon Lifecycle Management On Chip Architectures


Silicon lifecycle management (SLM) is transforming chip architectures, empowering designers to build smarter, more resilient, and secure semiconductor devices by leveraging data from manufacturing to end of life in the field. That data can be used to improve future designs, reduce margin, and continuously optimize performance and power efficiency throughout a chip's lifetime. Moreover, under... » read more

Faster Bug Discovery And Coverage Closure


Modern chip development is a complex process where functional verification often consumes a significant portion of project time and resources. Achieving efficient bug discovery and coverage closure is essential to prevent issues from reaching silicon. This white paper introduces an innovative approach using AI-powered Verification Space Optimization (VSO.ai) to enhance verification processes. ... » read more

Chip Industry Week In Review


China's Hefei Lumiverse Technology reportedly has developed a desktop-sized High Harmonic Generation light source that generates wavelengths as small as 1nm. One customer already has used it to produce 14nm chips, which was the original target node for EUV, according to one report. As a point of comparison, TSMC and Samsung didn't start using EUV until the 7nm node, relying instead on immersion... » read more

Adding Cost, Cycle Time, And Carbon Footprint To PPA Design Targets


When engineers start designing a new semiconductor technology and fabrication process, they set targets to define what they are trying to achieve to meet the market demands and beat competitive offerings. Traditionally, they have used the metrics of power, performance, and area (PPA). This post examines how additional design targets are mandated by today’s deep submicron nodes and how develop... » read more

New Panel Production Efforts Target Interposer Costs


The rising cost of increasingly large interposers is spurring renewed interest in panel-level manufacturing, which for years has hobbled along due to the massive and collective effort required by the chip industry to change formats. Several companies are developing their own processes, although there is currently no commercial production. And a new consortium called Joint3, spearheaded by Ja... » read more

Machine Learning Tools Accelerate Materials Discovery


Literature searches, simulations, and practical experiments have been part of the materials science toolkit for decades, but the last few years have seen an explosion of machine learning-driven software tools that promise to accelerate all three. Many of the challenges facing the semiconductor manufacturing industry are fundamentally materials science problems. What metal has the lowest resi... » read more

The Thermal Trap: How Dielectrics Limit Device Performance


The spread of artificial intelligence is forcing an uncomfortable truth on semiconductor manufacturing. Thin films, which are essential for isolating signals and insulating different components and metal layers, are becoming heat traps as physical dimensions continue to shrink in chips used inside AI data centers. That, in turn, is limiting how fast these chips can process data and increasing t... » read more

The Future For Formal Verification


Experts at the table: Semiconductor Engineering sat down to discuss possible future directions for formal verification technology with Ashish Darbari, CEO for Axiomise; Jin Zhang, product management group director for the Verification Group at Cadence; Sean Safarpour, executive director for R&D at Synopsys; and Jeremy Levitt, principal engineer for Digital Verification Technology at Siemen... » read more

Blog Review: Nov. 19


Cadence's Mamta Rana explores how Forward Error Correction in PCIe 6.0 is key to its 64.0 GT/s per lane bandwidth by enabling the receiver to detect and correct errors without retransmissions or protocol-level recovery by adding redundant information to transmitted data. Siemens' Dave Rich shares a paper from DVCon 1992 that introduced a new RTL modeling construct to Verilog, eventually know... » read more

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