Maximize Your Revenue With High-Speed Test Performance Optimization


In today’s competitive semiconductor market, revenue growth is often associated with design innovation, process advancements, or packaging breakthroughs. However, a powerful and frequently overlooked revenue lever lies much closer to production: high-speed test performance optimization. Test variability—particularly at high frequencies—can significantly influence product binning, yield... » read more

Enabling Seamless Monitoring, Test, And Repair In Multi-Die Designs


By Yervant Zorian and Sandeep Kumar Goel Anyone who follows the semiconductor industry knows that the accelerating performance, scale and energy efficiency demands of the AI revolution are outpacing the advances achievable by simply pushing the chip performance of monolithic, single-die designs. Multi-die design using 2.5D and 3D technologies has emerged as a necessity to keep the pace of in... » read more

Singulated Die Test Ensures Stacked Die Quality As Power Density Rises


The accelerating rate at which the industry adopts new process nodes is posing critical test challenges. Shrinking geometries combined with increased design complexity with respect to metrics such as gates per square micrometer, plus higher operating frequencies, are leading to ever higher levels of power density. The resulting device thermal excursions are driving the need for singulated die t... » read more

How AI Is Changing Computing And Why Testing Is Critical


Artificial intelligence (AI) is transforming industries, enhancing our daily lives, and improving efficiency and decision-making, but its need for compute processing power is growing at an astonishing rate, doubling every three months (Figure 1). To maintain this pace, the semiconductor industry is moving beyond traditional chip development – it has entered the era of heterogeneous chiplets i... » read more

Back-End Automation Tackles Growing Complexity


Experts at the table: Semiconductor Engineering sat down to discuss back-end automation challenges in advanced packaging with Michael Lowman, senior product marketing manager for Data Analytics at Cohu; Aftkhar Aslam, CEO at yieldWerx, Woo Young Han, product marketing director at Onto Innovation; and Lihong Cao, senior director of engineering and technical marketing for ASE. What follows are ex... » read more

Are You Using Structural Patterns In An SLT Environment?


Extending the in‑field life of your silicon is essential for long‑term success and for staying ahead of your competitors in today’s rapidly evolving digital world of data centers, automotive and cellular chipsets, and AI applications. For those reasons, it’s increasingly important to test your silicon in a System Level Test (SLT) environment. Testing in an SLT environment offers many be... » read more

Why Scan Diagnosis Should Be Part Of Every Fabless Company’s Yield Playbook


A fabless semiconductor company's world spins around two things, pushing design differentiation and getting those designs to market quickly and profitably. Yield isn’t just a manufacturing KPI. It's a business lever. And one of the most under-used levers in modern fabs is scan diagnosis, the practice of turning deterministic test infrastructure and failing test data into precise and action... » read more

High-Throughput Image Sensors: Smart Testing Powers Progress


In the race to produce higher resolution image sensors—now pushing beyond 500 megapixels—the industry faces significant challenges. These sensors aren’t just capturing more pixels; they’re handling massive streams of data, validating intricate on-chip AI functions, and doing it all at breakneck speeds. For manufacturers, the challenge is as unforgiving as it is critical: test more compl... » read more

Advanced Packaging: Driving Innovation, Performance, And New System Capabilities


Advanced packaging is no longer operating behind the scenes. The technology of advanced packaging is helping to sustain the speed of the semiconductor industry’s improvement in power and performance, even as the Moore’s Law roadmap for wafer-level scaling comes under strain. At the Advanced Packaging Conference during SEMICON Europa 2025 in Munich, global experts examined the growth tr... » read more

Scalable End-To-End Test Solutions For Today’s Complex SoCs


By Srikanth Venkat Raman and Sri Ganta Today’s highly complex and large system on chip (SoC) devices and systems present many challenges to be addressed from manufacturing tests to the field while meeting stringent requirements for test costs, test quality, yield, debug, and turn-around-times. Scalable and efficient end-to-end test solutions that scale to large and complex SoC design cores... » read more

← Older posts Newer posts →