tag: verification

Blog Review: Aug. 26
By Jesse Allen - 26 Aug, 2015 - Comments: 0

Synopsys' Marc Greenberg attended IDF and learned more about the newly announced Intel/Micron 3D XPoint memory technology named Optane including initial ship dates and some implementation details. In concluding his analysis of the 2014 Functional Verification Study, Mentor's Harry Foster reveals an unexpected finding about design size and respins. How do you keep your power grid from bein... » read more

Delivering Functional Verification Engagements
By Synopsys - 26 Aug, 2015 - Comments: 0

With the advent of smarter and higher performing devices, there has been a tremendous increase in design complexity. Driven by new high-end hardware feature and intelligent software requirements, these devices are comprised of multi-core processors and a multitude of interface IP, memory and other analog circuitry, communicating via many different interface protocols. This poses a huge challeng... » read more

Poised For Aspect-Oriented Design?
By Brian Bailey - 13 Aug, 2015 - Comments: 8

In 1992, [getperson id=" 11046 " comment="Yoav Hollander"] had the idea to take a software programming discipline called aspect-oriented programming (AOP) and apply it to the verification of hardware. Those concepts were incorporated into the [gettech id="31021" t_name="e"] language and [getentity id="22068" e_name="Verisity"] was formed to commercialize it. Hollander had seen that using obj... » read more

From Simulation To Emulation
By Mentor, a Siemens Business - 12 Aug, 2015 - Comments: 0

This paper introduces an acceleration-ready UVM framework and explains why it is needed, how to create it, and what its benefits are. By following the principles presented here, users will be able to write block-level UVM environments that can be reused directly in emulation. This approach has provided remarkable results in various customer environments, yielding a 50 to 5000X performance gain ... » read more

Making Hardware Design More Agile
By Ed Sperling - 12 Aug, 2015 - Comments: 1

Semiconductor engineering sat down to whether changes are needed in hardware design methodology, with Philip Gutierrez, ASIC/FPGA design manager in [getentity id="22306" comment="IBM"]'s FlashSystems Storage Group; Dennis Brophy, director of strategic business development at [getentity id="22017" e_name="Mentor Graphics"]; Frank Schirrmeister, group director for product marketing of the System ... » read more

Who’s Calling The Shots
By Ann Mutschler - 31 Jul, 2015 - Comments: 0

Throughout the PC era and well into the mobile phone market, it was semiconductor companies that called the shots while OEMs followed their lead and designed systems around chips. That’s no longer the case. A shift has been underway over the past half decade, and continuing even now, to reverse that trend. The OEM — or systems company as it is more commonly called today — now determine... » read more

Making Hardware Design More Agile
By Ed Sperling - 30 Jul, 2015 - Comments: 0

Semiconductor engineering sat down to whether changes are needed in hardware design methodology, with Philip Gutierrez, ASIC/FPGA design manager in [getentity id="22306" comment="IBM"]'s FlashSystems Storage Group; Dennis Brophy, director of strategic business development at [getentity id="22017" e_name="Mentor Graphics"]; Frank Schirrmeister, group director for product marketing of the System ... » read more

IP Verification Challenges
By Brian Bailey - 30 Jul, 2015 - Comments: 0

At the Design Automation Conference this year, the Designer and IP tracks were the stars of the show in many ways. These sessions catered to industry rather than academia and provided engineers with information they could directly use in their jobs. Many of the sessions were filled to capacity and Anne Cirkel, general chair for the 52nd DAC, was enthusiastic about the growing success of these t... » read more

7 Ways to Assess Semiconductor IP Quality
By Kurt Shuler - 30 Jul, 2015 - Comments: 0

Design teams today are struggling with the quality of semiconductor intellectual property. These teams want first-pass success for SoC creation, but that is becoming increasingly difficult to achieve—especially with highly configurable IP. Yet the more configurable the IP is, the more desirable it is as a differentiator. And if not developed correctly, it may be even more risky than non-confi... » read more

Accelerate SoC Simulation Time Of Newer Generation FPGAs
By Aldec - 29 Jul, 2015 - Comments: 0

Comprehensive verification that can be provided by HDL simulators is good, but not ideal. What is necessary is a faster, safer, and more thorough verification environment that combines the robustness of an HDL simulator with the speed of FPGA prototyping boards. The goal is to put together the power of these two verification methodologies into one platform. To read more, click here. » read more

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