tag: AI

Workload-Specific Hardware Accelerators
By Ed Sperling - 13 Aug, 2025 - Comments: 0

Workload-specific hardware accelerators are becoming essential in large data centers for two reasons. One is that general-purpose processing elements cannot keep up with the workload demands or latency requirements. The second is that they need to be extremely efficient due to limited electricity from the grid and the high cost of cooling these devices. Sharad Chole, chief scientist and co-foun... » read more

Building An AI Chip: Pre Silicon Planning
By Synopsys - 13 Aug, 2025 - Comments: 0

This white paper highlights the challenges of AI chip design, including balancing performance, cost, and power efficiency. It emphasizes the importance of early architecture exploration to avoid costly design revisions and ensure optimal power-performance trade-offs. The paper underscores the need for secure, efficient, and scalable IP solutions to meet the evolving demands of AI applications, ... » read more

The Painful Reality Of Scaling Cloud AI
By Alex Burlak - 12 Aug, 2025 - Comments: 0

The shift to Generative AI (GenAI) has overwhelmed existing infrastructure, transforming previously rare issues into daily operational realities. Skyrocketing costs, intense energy consumption, and hardware failures at unprecedented scales illustrate the strain of current AI workloads. With models like GPT-4 costing tens of millions and GPT-5 projected to surpass a billion-dollar threshold, the... » read more

What’s Different About HBM4
By Ed Sperling - 11 Aug, 2025 - Comments: 0

Memory bandwidth is limiting the flow of huge datasets that are needed to train AI models. There is much more data to process, store, and retrieve, but the speed at which that data moves through high-bandwidth memory (HBM) stacks is significantly lower than the speed at which data can be processed. Frank Ferro, group director for product management at Cadence, talks about the new HBM4 standard,... » read more

Security Tradeoffs: A Difficult Balance
By Ann Mutschler - 06 Aug, 2025 - Comments: 0

Experts At The Table: Semiconductor Engineering sat down to discuss hardware security challenges, including new threat models from AI-based attacks, with Nicole Fern, principal security analyst at Keysight; Serge Leef, AI-For-Silicon strategist at Microsoft; Scott Best, senior director for silicon security products at Rambus; Lee Harrison, director of Tessent Automotive IC Solutions at Sieme... » read more

Hallucination And Innovation At DAC
By Brian Bailey - 31 Jul, 2025 - Comments: 0

At DAC this year, I had the pleasure of moderating an intimate chat between Alon Shtepel, senior director for ASIC at Micron, and Abhi Kolpekwar, vice president and general manager for digital verification technology at Siemens EDA. The assigned topic was generative AI in design and verification, with the more provocative subtitle asking if we are hallucinating or innovating? L-R: Brian ... » read more

UEC-LLR: The Future Of Loss Recovery In Ethernet For AI And HPC
By Krunal Patel - 31 Jul, 2025 - Comments: 0

As Artificial Intelligence (AI) and High-Performance Computing (HPC) systems become the backbone of modern data centers, they generate and consume a massive amount of data. Traditional Ethernet was not built for such high-bandwidth traffic. In HPCs and AI models, computations are distributed across the nodes and the data is shared in real time with low latency and lossless communication. As ... » read more

Multi-Modal AI In EDA Development Flows
By Brian Bailey - 31 Jul, 2025 - Comments: 0

RTL coding is a critical step in the development of semiconductors, but many would argue it is not the most difficult. Things become a lot more complex as you get closer to implementation, and as the system context becomes larger than can be comprehended by text alone. In both cases, layout, timing, power, and many other factors come into play, but none is as easily represented by text, and the... » read more

How AI Will Impact Chip Design And Designers
By Ed Sperling - 31 Jul, 2025 - Comments: 1

Experts at the Table: Semiconductor Engineering sat down to discuss the role and impact of AI in chip design with Chuck Alpert, Cadence Fellow; Sathish Balasubramanian, head of product marketing and senior director for custom IC at Siemens EDA; Anand Thiruvengadam, senior director and head of AI product management at Synopsys; Sailesh Kumar, CEO of Baya Systems; Mehir Arora, head of engineering... » read more

Changes In Scan Test Data
By Ed Sperling - 29 Jul, 2025 - Comments: 0

Bigger designs with hundred of cores are creating an explosion in the volume of scan test data, significantly bumping up the amount of time spent on test. That raises the cost of test, forcing chipmakers to trade off higher costs with reliability. The solution is to raise the level of abstraction for scan tests, using a bus and packetized data that can run at much higher frequencies than is pos... » read more

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