tag: ANSYS

Design For Advanced Packaging
By Brian Bailey - 08 Nov, 2018 - Comments: 0

Advanced packaging techniques are viewed as either a replacement for Moore's Law scaling, or a way of augmenting it. But there is a big gap between the extensive work done to prove these devices can be manufactured with sufficient yield and the amount of attention being paid to the demands advanced packaging has on the design and verification flows. Not all advanced packaging places the same... » read more

How to Design, Optimize and Validate Safe Laser Headlamps Through Virtual Experimentation
By Ansys - 07 Nov, 2018 - Comments: 0

Today, car manufacturers and their suppliers are facing a real challenge: designing attractive laser headlamps that will illuminate the road without blinding drivers and pedestrians. Validating the safety of these headlight systems using physical prototypes would require millions of miles of night-driving testing and cost-prohibitive investment. Simulation is the only option for adequately a... » read more

Blog Review: Nov. 7
By Jesse Allen - 07 Nov, 2018 - Comments: 0

Arm's Shidhartha Das looks into maximizing the benefits of power delivery networks and explains a non-intrusive technique using an on-chip digital storage oscilloscope that can directly sample the power-rails to probe potential runtime bugs due to power delivery weaknesses. Synopsys' Snigdha Dua argues that scrambling is one of the most important features introduced in HDMI 2.0 and takes a l... » read more

Carmakers To Chipmakers: Where’s The Data?
By SE Staff - 24 Oct, 2018 - Comments: 0

The integration of electronics into increasingly autonomous vehicles isn't going nearly as smoothly as the marketing literature suggests. In fact, it could take years before some of these discrepancies are resolved. The push toward full autonomy certainly hasn't slowed down, but carmakers and the electronics industry are approaching that goal from very different vantage points. Carmakers and... » read more

Blog Review: Oct. 17
By Jesse Allen - 17 Oct, 2018 - Comments: 0

Arm's Shidhartha Das explores the challenges of power delivery in designing mobile systems and the importance of focusing on peak power consumption. Synopsys' Meenakshy Ramachandran explains the basics of Display Stream Compression and how it works to increase the effective bandwidth enabling support of high resolution displays. Cadence's Paul McLellan shares tips on more effective market... » read more

RISC-V: More Than a Core
By Brian Bailey - 15 Oct, 2018 - Comments: 2

The open-source RISC-V instruction set architecture (ISA) is attracting a lot of attention across the semiconductor industry, but its long-term success will depend on levels of cooperation never seen before in the semiconductor industry. The big question now is how committed the industry is to RISC-V's success. The real value that RISC-V brings is the promise of an ecosystem and the opportun... » read more

Week In Review: Design, Low Power
By Jesse Allen - 12 Oct, 2018 - Comments: 0

Deals AI startup Enflame (Suiyuan) Technology purchased multiple licenses of Arteris IP's FlexNoC interconnect IP for use as the on-chip communications backbone of its AI training chips for use in cloud datacenters. Enflame cited easy creation of regular topologies used in AI chips and the ability to take advantage of HBM2 memories. Phison, a maker of NAND flash controller ICs, inked�... » read more

Power Delivery Affecting Performance At 7nm
By Brian Bailey - 11 Oct, 2018 - Comments: 4

Complex interactions and dependencies at 7nm and beyond can create unexpected performance drops in chips that cannot always be caught by signoff tools. This isn't for lack of effort. The amount of time spent trying to determine if an advanced-node chip will work after it is fabricated has been rising steadily for several process nodes. Additional design rules handle everything from variation... » read more

Power Issues Grow For Cloud Chips
By Ann Mutschler - 11 Oct, 2018 - Comments: 0

Performance levels in traditional or hyperscale data centers are being limited by power and heat caused by an increasing number of processors, memory, disk and operating systems within servers. The problem is so complex and intertwined, though, that solving it requires a series of steps that hopefully add up to a significant reduction across a system. But at 7nm and below, predicting exactly... » read more

Reliability, Machine Learning And Advanced Packaging
By Ed Sperling - 11 Oct, 2018 - Comments: 0

Semiconductor Engineering sat down to discuss reliability, resilience, machine learning and advanced packaging with Rahul Goyal, vice president in the technology and manufacturing group at Intel; Rob Aitken, R&D fellow at Arm; John Lee, vice president and general manager of the semiconductor business unit at ANSYS; and Lluis Paris, director of IP portfolio marketing at TSMC. What follows ar... » read more

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