Cobalt To The Rescue


A big concern for chipmakers is a key part of the manufacturing flow—the backend-of-the-line (BEOL). In chip production, the BEOL is where the interconnects are formed within a device. Interconnects, those tiny wiring schemes in devices, are becoming more compact at each node. This, in turn, is causing a degradation in performance and an increase in the dreaded resistance-capacitance (RC) ... » read more

Blog Review: April 30


Applied Materials’ Jeremy Read points to a looming problem for the Internet of Things—legacy fabs that will require software upgrades and advanced process control. Also needed: Sensors attached to thousands of machines for predictive maintenance. Foundries are now ready for production finFETs. Cadence's Richard Goering captures the buzz at last week’s TSMC Tech Symposium, where the ro... » read more

Executive Insight: CH Wu


Semiconductor Engineering sat down with CH Wu, president and CEO of Advantest Taiwan, to talk about business, politics, and his philosophy on what really motivates people. What follows are excerpts of that conversation. SE: Tell us a little about who you are and your background. Wu: I graduated from college with a degree in electrical engineering and started at Philips Electric, then moved ... » read more

The Week In Review: Manufacturing


There is more evidence of a fab tool slowdown. In fact, ASML itself sounded the alarm during its earnings conference call this week. “ASML noted uncertainty regarding the timing of both the 16/14 nm finFET ramp at foundries (the company is seeing a delay from customers as the technology is still in development, in our view) and 3D NAND,” said Weston Twigg, an analyst from Pacific Crest Secu... » read more

What If EUV Fails?


It’s the worst kept secret in the industry, but extreme ultraviolet (EUV) lithography will likely miss the 10nm node. So, chipmakers will likely extend and use today’s 193nm immersion lithography down to 10nm. This, of course, will require a complex and expensive multiple patterning scheme. Now, chipmakers are formulating their lithography strategies for 7nm and beyond. As it stands now,... » read more

Time To Revisit 2.5D And 3D


Chipmakers are reaching various and challenging inflection points. In logic, many IC makers face a daunting transition from planar transistors at 20nm to finFETs at 14nm. And on another front, the industry is nearing the memory bandwidth wall. So perhaps it’s time to look at new alternatives. In fact, chipmakers are taking a hard look, or re-examining, one alternative—stacked 2.5D/3D chi... » read more

Favorite Forecast Fallacies


It’s difficult to make predictions, especially about the future. – An Old Danish Proverb. The GSA Silicon Summit was held on Thursday, April 10th at the Computer History Museum in Mountain View, CA. The opening panel session was entitled Advancements in Nanoscale Processing. The panelists were Rob Aitken (ARM), Adam Brand (Applied Materials), Peter Huang (TSMC), Nick Kepler (VLSI Researc... » read more

The Week In Review: Manufacturing


Don't look now, but the fab tool market is slowing. "After recent meetings in the supply chain plus examining comments from the largest spenders, we conclude that wafer fab equipment (WFE) could disappoint this year. We calculate approximately $30 billion to $31 billion in WFE spending in 2014, flattish from 2013, compared to expectations of $32 billion to $33 billion, which would be up 10%+. T... » read more

The Week In Review: Manufacturing


GlobalFoundries has emerged as the leading candidate to buy IBM's semiconductor unit, according to Reuters, which cited the Wall Street Journal as it source. IBM, which recently put its semiconductor unit on the block, has held discussions with GlobalFoundries, Intel and Taiwan Semiconductor Manufacturing Co. Ltd. GlobalFoundries did not respond to the reports by press time. GlobalFoundries ... » read more

Blog Review: April 2


Mentor’s Nazita Saye compares roadway roundabouts to networked systems. One roundabout works fine, but add in a bunch of them and you have a massive traffic jam. How many roundabouts are in your design? Cadence’s Richard Goering interviews Stan Kroliskoski, chair of the IEEE Design Automation Standards Committee, about four working groups on EDA standards and what’s ahead. Speaking ... » read more

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