Chip Industry Week in Review


Intel hired ex-Qualcomm GPU guru Eric Demers for the company's high-performance GPU push, setting the stage for a three-way battle with Nvidia and AMD. The key targets for Intel and AMD will be better power efficiency and a programming model that rivals CUDA, but don't expect Nvidia to stand still. Acquisitions Texas Instruments plans to acquire Silicon Labs for ~$7.5B cash to enhance i... » read more

Blog Review: Feb. 4


Siemens' Tova Levy examines thermal management in 3D-IC, including why heat behaves differently in vertical stacks and how to analyze and manage thermal risk earlier and more predictably to ensure a design can meet performance, reliability, and time-to-market targets. Cadence's Reela Samuel finds that known-good-die strategies, standardized die-to-die test access, and vertical reliability mo... » read more

Blog Review: Jan. 28


Synopsys' Dana Neustadter and Vincent van der Leest argue that a hardware-based approach to security is required to fully address the risks introduced by modern AI architectures and the distributed workloads they support. Siemens EDA's Tova Levy examines multiphysics challenges in 3D-IC designs and outlines three design imperatives to identify risks earlier and support PPA, reliability, and ... » read more

Blog Review: Jan. 21


Keysight's Armando Valim considers the impact of AI on the memory market as AI infrastructure pressure widens the gap between high-performance memory and lower-margin consumer memory and SSD, forcing manufacturers to make strategic decisions and define which markets to serve. Cadence's Reela Samuel breaks down the major 3D-IC packaging methods used today, from wafer stacking flows to hybrid ... » read more

Chip Industry Week in Review


Geopolitics Taiwan and the U.S. signed a trade agreement this week, with TSMC and other Taiwanese companies collectively pledging to directly invest at least $250B in investments in advanced semiconductor, energy and AI production and capacity in the U.S.  The agreement also included Taiwan providing another $250B in credit guarantees for additional IC supply chain expansions in the U.S., cap... » read more

Smarter Write Barriers For Arm64 In .NET CoreCLR


Last year, I explored how you can use the Arm Scalable Vector Extension (SVE) in .NET to unlock SIMD performance at scale. This year, my focus has shifted to something less visible but just as fundamental to runtime performance. Write barriers in the CoreCLR garbage collector (GC). Write barriers are not a feature most .NET developers ever think about. They do not change how you write C# cod... » read more

Blog Review: Jan. 14


Arm's Paul Black demonstrates how lightweight LLVM sanitizers help detect undefined behavior, improve code quality, and expose hidden bugs in embedded C and C++ projects, with a focus on two sanitizers that can catch issues such as unsigned signed shift overflows, array overflows, and stack corruption. Imagination's Alex Pim provides an overview of LLM inference acceleration for mobile and e... » read more

Chip Industry Week in Review


SIA's latest monthly global semiconductor sales report reflects a ~30% YOY increase, hitting a record $75.3B in November 2025. Asia Pacific had a notable 66% increase. Cadence launched its Chiplet Spec-to-Packaged Parts ecosystem to accelerate time to market for chiplet development for physical AI, data centers, and HPC applications. Initial IP partners joining Cadence include Arm, Arteris, ... » read more

Is End-To-End Security Possible?


Looming financial penalties for data breaches are forcing chipmakers to confront end-to-end security, an increasingly complex and daunting problem because no single company controls all the pieces anymore. This is especially apparent in multi-die assemblies, in use today in data centers, and under consideration in automotive and other applications. Multiple chiplets can push performance well... » read more

Blog Review: Jan. 7


Cadence's Reela Samuel presents an overview of through-silicon vias, including structure, pitch, and electrical behavior, key layout rules such as keep-out zones and stress constraints, and how TSV parasitics influence bandwidth, latency, and system-level performance. Siemens' Andras Vass-Varnai identifies five thermal trends to watch and how they’ll reshape design and packaging workflows ... » read more

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