tag: Arteris

The Growing Verification Challenge
By Ed Sperling - 28 Nov, 2012 - Comments: 0

System-Level Design talks with Charles Janac of Arteris, Frank Schirrmeister of Cadence, Venkat Iyer of Uniquify and Adnan Hamid of Breker Verification Systems about the growing difficulty of verifying complex SoCs and what lies ahead. [youtube vid=zUB4_t9teE8] » read more

Quantum Shifts
By Ed Sperling - 25 Oct, 2012 - Comments: 0

By Ed Sperling Intel, STMicroelectronics and some of the leading memory providers already are working on 10nm process technology, and advanced researchers in universities and industry-leading companies are looking at 7nm, 5nm and even beyond. Those who have glimpsed this technological future have similar observations. There is no single technology problem that has to be solved at these node... » read more

Putting The “Heterogeneous” In The HSA Foundation
By Kurt Shuler - 25 Oct, 2012 - Comments: 0

By Kurt Shuler In last month’s article I explained why symmetric multiprocessing (SMP) architectures have been popular in PC and server markets, and why heterogeneous or asymmetric multiprocessing (AMP) has been the norm in mobility and consumer electronics markets. I also explained the trends that are leading PC and server markets to adopt heterogeneous architectures and introduced the HSA ... » read more

The Increasing Challenge Of Reducing Latency
By Ed Sperling - 11 Oct, 2012 - Comments: 0

By Ed Sperling When the first mainframe computers were introduced the big challenge was to improve performance by decreasing the latency between spinning reels of tape and the processor—while also increasing the speed at which the processor could crunch ones and zeroes. Fast forward more than six decades and the two issues are now blurred and often confused. Latency is still a drag on per... » read more

Thanks For The Memories
By Ed Sperling - 27 Sep, 2012 - Comments: 0

By Ed Sperling The amount of real estate in a design now devoted to memories—SRAM on chip, DRAM off chip, and a few other more exotic options showing up occasionally—is a testament to the amount of data that needs to be utilized quickly in both mobile and fixed devices. Memory is almost singlehandedly responsible for the routing congestion now plaguing complex SoCs. It is one of the mai... » read more

SMP, Asymmetric Multi- processing And The HSA Foundation
By Kurt Shuler - 27 Sep, 2012 - Comments: 0

When we hear the term “multiprocessing,” we often associate it with “symmetric multiprocessing (SMP).” This is because of SMP’s initial prevalence in the high-performance computing world, and now in x86/x64 servers and PCs. However, it’s been known for years that SMP’s ability to scale performance as the number of cores increases is poor. (For more information on SMP’s inability... » read more

Inflection Points Ahead
By Ed Sperling - 23 Aug, 2012 - Comments: 0

By Ed Sperling Engineering challenges have existed at every process node in semiconductor designs, but at 20nm and beyond, engineers and executives on all sides of the industry are talking about inflection points. An inflection point is literally the place where a curve on a graph turns down or up, but in the semiconductor industry it’s usually associated with the point at which a progres... » read more

Being Different Is Bad
By Ed Sperling - 23 Aug, 2012 - Comments: 0

By Ann Steffora Mutschler Today’s SoCs contain as much as 80% existing IP that either has been re-used from previous projects or obtained from a third party. Models are created of this hardware IP, as well as new portions of the design, in order to create a virtual prototype that allows the engineering team to see the complete system by running software and applications. While this a... » read more

From Hype To Reality
By Kurt Shuler - 23 Aug, 2012 - Comments: 0

By Kurt Shuler My purpose in this article is to explain Gartner Research’s Hype Cycle and relate it to the Technology Adoption Lifecycle popularized by Geoffrey Moore’s book, “Crossing the Chasm.” These two models can be used together to provide a combined picture of market expectations and expected technology adoption rates, but people often get the timeframes and takeaways wrong. So ... » read more

Experts At The Table: Pain Points
By Ed Sperling - 27 Jul, 2012 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down with Vinod Kariat, a Cadence fellow; Premal Buch, vice president of software engineering at Altera; Vic Kulkarni, general manager of Apache Design; Bernard Murphy, CTO at Atrenta, and Laurent Moll, CTO at Arteris. What follows are excerpts of that conversation. LPHP: What comes next requires a lot of guesswork in the design, do... » read more

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