tag: Arteris

Routing Congestion Returns
By Ed Sperling - 26 Jul, 2012 - Comments: 0

By Ed Sperling Routing congestion has returned with a vengeance to SoC design, fueled by the advent of more third-party IP, more memory, a variety of new features, as well as the inability to scale wires at the same rate as transistors. This is certainly not a foreign concept for IC design. The markets for place and route tools were driven largely by the need to automate this kind of operat... » read more

SoC Platforms Gain Steam
By Ed Sperling - 26 Jul, 2012 - Comments: 0

By Ed Sperling Platforms are attracting far more attention from makers of SoCs because they are pre-verified and can speed time to market, but the shift isn’t so simple. It will spark major changes in the way companies design and build chips, causing significant disruption across the entire SoC ecosystem. Platforms are nothing new in the processor and software world. Intel, IBM AMD, and N... » read more

Who Calls The Shots?
By Kurt Shuler - 26 Jul, 2012 - Comments: 0

By Kurt Shuler Who REALLY calls the shots in chip design today? That sounds like a stupid question. Who really calls the shots in chip design today? Well, chip designers of course. But you’re wrong if you mean to say that the traditional semiconductor manufacturers are the ones who always do all the hefty work of chip design, including determining requirements, performing technical tra... » read more

Experts At The Table: Pain Points
By Ed Sperling - 20 Jul, 2012 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down with Vinod Kariat, a Cadence fellow; Premal Buch, vice president of software engineering at Altera; Vic Kulkarni, general manager of Apache Design; Bernard Murphy, CTO at Atrenta, and Laurent Moll, CTO at Arteris. What follows are excerpts of that conversation. LPHP: With stacked die it’s no longer one company making an SoC. W... » read more

Experts At The Table: Pain Points
By Ed Sperling - 12 Jul, 2012 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down with Vinod Kariat, a Cadence fellow; Premal Buch, vice president of software engineering at Altera; Vic Kulkarni, general manager of Apache Design; Bernard Murphy, CTO at Atrenta, and Laurent Moll, CTO at Arteris. What follows are excerpts of that conversation. LPHP: Where will the pain points be going forward? Kariat: 20nm is... » read more

Roundtable: DAC Retrospective
By Ed Sperling - 13 Jun, 2012 - Comments: 0

Is DAC really a design automation conference, or has it shifted to a design enablement conference due to rising complexity breaking down traditional barriers and silos? Low Power High Performance Engineering talks with Atrenta CTO Bernard Murphy about the changes. [youtube vid=Z_xBaRsC_Hs] » read more

What’s On TV?
By Kurt Shuler - 24 May, 2012 - Comments: 0

By Kurt Shuler Could Apple TV revive the digital TV (DTV) market? That was the underlying question behind a trio of presentations given at yesterday’s Gartner Semiconductor Briefing at in San Jose. Three Gartner analysts outlined a path forward for our industry to innovate its way out of the morass that has become the digital TV market. Alfonso Velosa was the first analyst to present a... » read more

NoC Power Benefits
By Various Writers - 24 May, 2012 - Comments: 0

The system-on-chip (SoC) interconnect spans the entire floorplan of a chip and consumes a significant portion of the power. The interconnects of today’s SoCs are a distributed architecture of switches, buffers, firewalls, register slices, and clock and power domain crossings. One approach is to implement these units modularly with a simple, universal transport protocol between all units... » read more

Tech Talk: Coherency’s Next Frontiers
By Ed Sperling - 23 May, 2012 - Comments: 0

Laurent Moll, CTO of Arteris, talks about new types of coherency and why it will be such a big challenge. [youtube vid=lufY9yDLjwE] » read more

Experts At The Table: Hardware-Software Co-Design
By Ed Sperling - 11 May, 2012 - Comments: 0

By Ed Sperling System-Level Design sat down to discuss hardware-software co-design with Frank Schirrmeister, group marketing director for Cadence’s System and Software Realization Group; Shabtay Matalon, ESL market development manager at Mentor Graphics; Kurt Shuler, vice president of marketing at Arteris; Narendra Konda, director of hardware engineering at Nvdia; and Jack Greenbaum, direct... » read more

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