tag: Cadence Design Systems

Week in Review – IoT, Security, Autos
By Jeff Dorsch - 04 Oct, 2019 - Comments: 0

Products/Services Cadence Design Systems is working with Adesto Technologies to grow the Expanded Serial Peripheral Interface (xSPI) communication protocol ecosystem, for use in Internet of Things devices. The Cadence Memory Model for xSPI allows customers to ensure optimal use of the octal NOR flash with the host processor in an xSPI system, including support for Adesto’s EcoXiP octal xSPI ... » read more

Week in Review – IoT, Security, Autos
By Jeff Dorsch - 27 Sep, 2019 - Comments: 0

Products/Services Achronix Semiconductor joined Taiwan Semiconductor Manufacturing’s IP Alliance Program, part of the foundry’s Open Innovation Platform. Achronix’s Speedcore eFPGA IP is available today on TSMC 16nm FinFET Plus (16FF+) and N7 process technologies, and it will be soon available on TSMC 12nm FinFET Compact Technology (12FFC). Cadence Design Systems announced that its di... » read more

Celsius Thermal Solver
By Cadence - 25 Sep, 2019 - Comments: 0

The Celsius Thermal Solver environment enables all aspects of thermal analysis to quickly and accurately identify thermal problems in IC packages, PCBs, and electronics systems. It features an innovative massive parallel solver technology that enables simulation speeds up to 10 times faster than conventional thermal simulators, with significantly reduced memory usage. It includes a powerful fin... » read more

Week in Review – IoT, Security, Autos
By Jeff Dorsch - 20 Sep, 2019 - Comments: 0

Products/Services Synopsys had a lot of announcements this week! Summer is definitely over. The company released BSIMM10 study, the latest version of the Building Security in Maturity Model, helping organizations plan, execute, mature, and measure their software security initiatives. It also released LucidShape version 2019.09, the latest version of that tool for the design, simulation, and an... » read more

A Complete System-Level Security Verification Methodology
By Cadence - 04 Sep, 2019 - Comments: 0

Hardware is at the root of all digital systems, and security must be considered during the system-on-chip (SoC) design and verification process. Verifying the security of an SoC design is challenging because of time to market pressure and resource constraints. Resources allocated to the already time-consuming task of functional verification must be diverted to security verification, which requi... » read more

Week in Review: IoT, Security, Autos
By Jeff Dorsch - 09 Aug, 2019 - Comments: 0

Products/Services Synopsys agreed to acquire QTronic, a German company specializing in simulation, test tools, and services for automotive software and systems development. The transaction is expected to close in the fourth quarter of the company’s 2019 fiscal year. “The terms of the deal, which is not material to Synopsys financials, are not being disclosed,” Synopsys said in a statemen... » read more

Debugging Complex SoCs
By Brian Bailey - 27 Jun, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss the debugging of complex SoCs with Randy Fish, vice president of strategic accounts and partnerships for UltraSoC; Larry Melling, product management director for Cadence; Mark Olen, senior product marketing manager for Mentor, a Siemens Business; and Dominik Strasser, vice president of engineering for OneSpin Solutions. What follows are excerpts of ... » read more

HBM2 Vs. GDDR6: Tradeoffs In DRAM
By Ed Sperling - 13 Jun, 2019 - Comments: 0

Semiconductor Engineering sat down to talk about new DRAM options and considerations with Frank Ferro, senior director of product management at Rambus; Marc Greenberg, group director for product marketing at Cadence; Graham Allan, senior product marketing manager for DDR PHYs at Synopsys; and Tien Shiah, senior manager for memory marketing at Samsung Electronics. What follows are excerpts of th... » read more

Revolution By Evolution: Getting To The Next Technology Breakthrough In Analog Simulation
By Cadence - 12 Jun, 2019 - Comments: 0

Recent technology developments, advanced-node adoptions, and Moore than Moore designs have forced analog and custom IC designers to adopt new design practices that benefit from these advancements. These changes have resulted in the need to simulate larger designs with more post-layout parasitics. In addition, many custom IC designs such as flash memory, MRAM, sensor arrays, etc., now require SP... » read more

The Changing Landscape of Hardware-Based Verification And Software Development
By Frank Schirrmeister - 24 May, 2019 - Comments: 0

As the EDA is gearing up for its biggest industry event, the Design Automation Conference (DAC), this year in Las Vegas, it is interesting to observe what is going on in hardware-based development of emulation and prototyping. The trends I had outlined after last DAC in 2018—system design, cloud, and machine learning—have only grown stronger and are causing changes in the development landsc... » read more

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