Software-Driven and System-Level Tests Drive Chip Quality


Traditional semiconductor testing typically involves tests executed by automatic test equipment (ATE). But engineers are beginning to favor an additional late-test pass that tests systems-on-chip (SoCs) in a system context in order to catch design issues prior to end-product assembly. “System-level test (SLT) gives a high-volume environment where you can test the hardware and software toge... » read more

Week In Review: Auto, Security, Pervasive Computing


From pandemic to war — some of the news this week highlights reactions to Russia’s invasion of Ukraine. Pervasive computing, IoT, 5G and beyond SpaceX sent Starlink satellite dishes to Ukraine to enable Ukrainian access to the Internet. The caveat is the uplink signals from satellite equipment can be used to triangulate the position of the dish, which can then be hit by missile. The dis... » read more

Verifying Side-Channel Security Pre-Silicon


As security grows in importance, side-channel attacks pose a unique challenge because they rely on physical phenomena that aren’t always modeled for the design verification process. While everything can be hacked, the goal is to make it so difficult that an attacker concludes it isn't worth the effort. For side-channel attacks, the pre-silicon design is the best place to address any known ... » read more

Internet Tech Trends For 2022


Every year at the start of the year, Benedict Evans produces a big presentation on trends in technology, internet, mobile, and so on. He used to live in the US and did this for Andreesen-Horowitz (a16z), but he has since returned to Britain (he's English) and I think has his own consulting company. This year's presentation is titled "Three Steps to the Future." The most exciting themes in t... » read more

Preparing For Test Early In The Design Flow


Until very recently, semiconductor design, verification, and test were separate domains. Those domains have since begun to merge, driven by rising demand for reliability, shorter market windows, and increasingly complex chip architectures. In the past, products were designed from a functional perspective, and designers were not concerned about what the physical implementation of the product ... » read more

Blog Review: March 2


Arm's Charlotte Christopherson checks out SpiNNaker1, a project to develop a massively parallel, manycore supercomputer architecture that mimicked the interactions of biological neurons, and its follow up, SpiNNaker2, a hybrid system that combines statistical AI and neuromorphic computing. Cadence's Paul McLellan looks at open and generic PDKs that can be used by researchers and in education... » read more

Week In Review: Design, Low Power


Tools & IP Codasip debuted two new customizable low power embedded RISC-V processor cores. To support embedded AI applications, the L31/L11 cores run Google’s TensorFlowLite for Microcontrollers. Codasip Studio tools can be used to customize for specific system, software, and application requirements. Licensing the CodAL description of a Codasip RISC-V core grants customers a full archit... » read more

Week In Review: Auto, Security, Pervasive Computing


Security Fraunhofer IIS received a grant to establish an R&D center for trustworthy integrated electronic systems for security and safety. Working with other Fraunhofer divisions, Fraunhofer IIS will use innovative methods in design and testing to help protect IP along the value chain of microelectronic components and systems. The center will focus on creating a secure design flow for inte... » read more

Data Center Architectures In Flux


Data center architectures are becoming increasingly customized and heterogeneous, shifting from processors made by a single vendor to a mix of processors and accelerators made by multiple vendors — including system companies' own design teams. Hyperscaler data centers have been migrating toward increasingly heterogeneous architectures for the past half decade or so, spurred by the rising c... » read more

Unintended Coupling Issues Grow


The number of indirect and often unexpected ways in which one design element may be affected by another is growing, making it more difficult to ensure a chip — or multiple chips in a package — will perform reliably. Long gone are the days when the only way that one part of a circuit could influence another was by an intended wire connecting them. As geometries get smaller, frequencies go... » read more

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