tag: Cadence

Week In Review: Design, Low Power
By Jesse Allen - 11 Dec, 2020 - Comments: 0

RISC-V RISC-V International CEO Calista Redmond provided an update on the state of the community during the annual RISC-V Summit: “RISC-V has had an incredible year of growth and momentum. This year, our technical community has grown 66 percent to more than 2,300 individuals in our more than 50 technical and special interest groups. We’re seeing increased market momentum of RISC-V cores, S... » read more

Week In Review: Auto, Security, Pervasive Computing
By SE Staff - 11 Dec, 2020 - Comments: 0

Automotive Self-driving car company Cruise now has driverless cars on the streets of San Francisco, Calif., reports the San Francisco Chronicle. Cruise, which is backed by General Motors, is testing five driverless cars in the urban — and very hilly — environment of San Francisco. Cruise is using an EV — the Chevy Bolt — as a test vehicle. At Level 4 driving, the cars will not have a w... » read more

Re-Architecting SerDes
By Brian Bailey - 10 Dec, 2020 - Comments: 0

Serializer/Deserializer (SerDes) circuits have been helping semiconductors move data around for years, but new process technologies are forcing it to adapt and change in unexpected ways. Traditionally implemented as an analog circuit, SerDes technology has been difficult to scale, while low voltages, variation, and noise are making it more difficult to yield sufficiently. So to remain releva... » read more

Low Power Still Leads, But Energy Emerges As Future Focus
By Ann Mutschler - 10 Dec, 2020 - Comments: 1

In 2021 and beyond, chips used in smartphones, digital appliances, and nearly all major applications will need to go on a diet. As the amount of data being generated continues to swell, more processors are being added everywhere to sift through that data to determine what's useful, what isn't, and how to distribute it. All of that uses power, and not all of it is being done as efficiently as... » read more

Attaching Fibers To Photonic Chips
By Paul McLellan - 10 Dec, 2020 - Comments: 0

Recently, Cadence held its fifth photonics summit, CadenceCONNECT: Photonics Contribution to High-Performance Computing. You can read my earlier posts: Photonic Integration—From Switching to Computing How to Design Photonics If You Don't Have a PhD: iPronics and Ayar Labs The third day was all about how to connect the incoming and outgoing fibers to the photonics chips. I will cov... » read more

Waking And Sleeping Create Current Transients
By Bryon Moyer - 10 Dec, 2020 - Comments: 0

Silicon power-saving techniques are helping to reduce the power required by data centers and other high-intensity computing environments, but they’ve also added a significant challenge for design teams. As islands on high-powered chips go to sleep and wake up, the current requirements change quickly. This happens in a few microseconds, at most. The rapid change of loading creates a challen... » read more

Blog Review: Dec. 9
By Jesse Allen - 09 Dec, 2020 - Comments: 0

Arm's Benoit Labbe digs into designing a power converter for Arm Research's ultra-low power M0N0 microcontroller, with a focus on optimal efficiency and leakage constraints. Mentor's Harry Foster tries to get a sense of how much effort is spent in verification of FPGAs by looking at the amount of time spent and number of engineers on a project. Cadence's Paul McLellan listens in as Odile ... » read more

How To Speed Up Large-Scale EM Simulation Of ICs Without Compromising Accuracy
By Cadence - 09 Dec, 2020 - Comments: 0

With growing on-chip radio frequency (RF) content, electromagnetic (EM) simulation of the passives is critical for a variety of reasons — from selecting the right RF design candidates to detecting parasitic coupling that directly impacts performance. Being on-chip, accurate EM analysis requires a tie into the process technology in the form of process design kits (PDKs) as well as a foundry-ce... » read more

Digital Test Bulks Up – Or Down
By Bryon Moyer - 08 Dec, 2020 - Comments: 2

Large digital integrated circuits are becoming harder to test in a time- and cost-efficient manner. AI chips, in particular, have tiled architectures that are putting pressure on older testing strategies due to the volume of test vectors required. In some cases, these chips are so large that they exceed reticle size, requiring them to be stitched together. New testing efficiencies are needed... » read more

Test Engineers In Very Short Supply
By SE Staff - 08 Dec, 2020 - Comments: 2

Semiconductor design, verification, manufacturing, and test requires an army of engineers, with each playing a special role. But increasingly, these disciplines also require additional training to be able to understand the context around their jobs, and that is making it harder to fill different positions at a time when the chip industry already is severely short-staffed. This is particularl... » read more

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