tag: Cadence

Blog Review: Oct. 21
By Jesse Allen - 21 Oct, 2020 - Comments: 0

Rambus' Frank Ferro and IDC's Shane Rau compare the evolution of HBM and GDDR6, as well as the design tradeoffs and challenges of the two memory types. Mentor's Neil Johnson compares unit testing and formal property checking as first steps for verifying low-level RTL functionality. Synopsys' Patrick Carey considers the competing demands of delivering a product as soon as possible and maki... » read more

Increase In Analog Problems
By Brian Bailey - 19 Oct, 2020 - Comments: 6

Analog and mixed signal design has always been tough, but a resent survey suggests that the industry has seen significantly increased failures in the past year because the analog circuitry within an ASIC was out of tolerance. What is causing this spike in failures? Is it just a glitch in the data, or are these problems real? The answer is complicated, and to a large extent it depends heavily... » read more

Week In Review: Design, Low Power
By Jesse Allen - 16 Oct, 2020 - Comments: 0

Tools & IP Cadence debuted System-Level Verification IP (System VIP), a suite of tools and libraries for automating SoC testbench assembly, bus and CPU traffic generation, cache-coherency validation, and system performance bottleneck analysis. Tests created using the System VIP solution are portable across Cadence simulation, emulation and prototyping engines and can also be extended to po... » read more

Week In Review: Auto, Security, Pervasive Computing
By SE Staff - 16 Oct, 2020 - Comments: 0

Security Intel announced new security features for its code-named Ice Lake CPU, according to a story in SecurityWeek. The 10nm-based Xeon Scalable will have SGX trusted execution environment and several new features for memory encryption, firmware resilience, and cryptographic performance acceleration. The new Total Memory Encryption (TME) feature in the CPU will encrypt access to memory. S... » read more

Slower Metal Bogs Down SoC Performance
By Bryon Moyer - 15 Oct, 2020 - Comments: 0

Metal interconnect delays are rising, offsetting some of the gains from faster transistors at each successive process node. Older architectures were born in a time when compute time was the limiter. But with interconnects increasingly viewed as the limiter on advanced nodes, there’s an opportunity to rethink how we build systems-on-chips (SoCs). ”Interconnect delay is a fundamental tr... » read more

Searching For Power Bugs
By Brian Bailey - 15 Oct, 2020 - Comments: 0

How much power is your design meant to consume while performing a particular function? For many designs, getting this right may separate success from failure, but knowing that right number is not as easy as it sounds. Significant gaps remain between what power analysis may predict and what silicon consumes. As fast as known gaps are closed, new challenges and demands are being placed on the ... » read more

Testing For Electromagnetic Compliance Without An Anechoic Chamber
By Paul McLellan - 15 Oct, 2020 - Comments: 0

You can't sell an electronic product without getting CE or FCC (or equivalent) certification. In fact, for medical devices and aerospace, the requirements are even stricter. This doesn't just apply to obvious electronic products like laptops or automotive ECUs (electronic control units). It even applies to household goods like washers and dryers. Furthermore, this isn't just some sort of nice-t... » read more

Confusion Grows Over Packaging And Scaling
By Ann Mutschler - 15 Oct, 2020 - Comments: 0

The push toward both multi-chip packaging and continued scaling of digital logic is creating confusion about how to classify designs, what design tools work best, and how to best improve productivity and meet design objectives. While the goals of design teams remains the same — better performance, lower power, lower cost — the choices often involve tradeoffs between design budgets and ho... » read more

Blog Review: Oct. 14
By Jesse Allen - 14 Oct, 2020 - Comments: 0

Arm's Hongsup Shin explains a machine learning application that can determine which tests are most likely to find hardware bugs, improving efficiency and reducing the number of tests that need to be run. Synopsys' Pieter van der Wolf and Dmitry Zakharov take a look at the increasing need for low power processors optimized for machine learning tasks as IoT, smart home, and wearable devices pr... » read more

Scramble For The White Space
By Bryon Moyer - 13 Oct, 2020 - Comments: 0

Chipmakers are pushing to utilize more of the unused portion of a design for different functions, reducing margin in the rest of the chip to more clearly define that white space. White space typically is used to relieve back-end routing congestion before all of the silicon area is used up. But a significant amount of space still remain unused. That provides an opportunity for inserting monit... » read more

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