tag: Cadence

A Guide To Accelerating Your Design Timeline With Electromagnetic Analysis
By Cadence - 12 Nov, 2025 - Comments: 0

Today’s high-speed PCB and system-level design demands fast, accurate simulation. This ebook explains how to choose the right electromagnetic (EM) solver—from 2D and hybrid methods to full 3D FEM—for every stage of the design process. Inside, you’ll learn: When to use 2D, 3D planar (hybrid), or full-wave 3D solvers How the cloud-native parallelized Cadence Clarity 3D Tran... » read more

LLMs Add Safety Risks To Physical AI
By Liz Allan - 06 Nov, 2025 - Comments: 0

Humanoid robots with artificial general intelligence are some years from entering our daily life, but application-specific robotics are already here. From Amazon’s fleet of fulfillment center robots to robotic surgical systems in operating rooms, search and rescue robo-dogs, autonomous drones, and last-mile delivery robots, all the way down to the humble Roomba vacuum cleaner, physical AI sys... » read more

Moving AI Workloads To The Edge
By Ann Mutschler - 06 Nov, 2025 - Comments: 0

Experts At The Table: Semiconductor Engineering gathered a group of experts to discuss how some AI workloads are better suited for on-device processing to achieve consistent performance, avoid network connectivity issues, reduce cloud computing costs, and ensure privacy. The panel included Frank Ferro, group director in the Silicon Solutions Group at Cadence; Eduardo Montanez, vice president an... » read more

Innovation In Data Center Design And Operations
By Veena Parthan - 06 Nov, 2025 - Comments: 0

As artificial intelligence (AI) continues to advance, data centers are evolving into dynamic command hubs designed to handle the massive data throughput and processing power required for advanced AI applications. These facilities are no longer just storage units; they are transforming into intelligent, self-optimizing "AI factories" that redefine efficiency and capability. Recently, we had the ... » read more

Formal Verification’s Value Grows
By Brian Bailey - 05 Nov, 2025 - Comments: 0

Experts at the table: Semiconductor Engineering sat down to discuss why formal verification is becoming more important, with Ashish Darbari, CEO for Axiomise; Jin Zhang, product management group director for the Verification Group at Cadence; Sean Safarpour, executive director for R&D at Synopsys; and Jeremy Levitt, principal engineer for Digital Verification Technology at Siemens EDA. Wha... » read more

Blog Review: Nov. 5
By Jesse Allen - 05 Nov, 2025 - Comments: 0

Synopsys' Igor Markov points out how numerical simulation tools advance quantum computing R&D by capturing both quantum-mechanical behavior and classical electromagnetic effects so researchers can evaluate design alternatives before fabrication and gain insight into how devices operate under realistic conditions. Siemens' Stephen V. Chavez finds that impedance modeling and control are mi... » read more

LPDDR6: Not Just For Mobile Anymore
By Ed Sperling - 03 Nov, 2025 - Comments: 0

LPDDR memory has been almost synonymous with mobile devices, but starting with the new LPDDR6 specification released in July 2025 by JEDEC, it will begin showing up inside of data centers, as well, early next year. The key factors in various flavors of DRAM are bandwidth, capacity, and cost. HBM is the fastest, but it's also expensive, and it requires a 2.5D or 3.5D packaging approach. GDDR is ... » read more

Small Vs. Large Language Models
By Ed Sperling - 03 Nov, 2025 - Comments: 0

The proliferation of edge AI will require fundamental changes in language models and chip architectures to make inferencing and learning outside of AI data centers a viable option. The initial goal for small language models (SLMs) — roughly 10 billion parameters or less, compared to more than a trillion parameters in the biggest LLMs — was to leverage them exclusively for inferencing. In... » read more

Chip Industry Week in Review
By The SE Staff - 31 Oct, 2025 - Comments: 0

San Francisco-based Substrate raised more than $100 million to build a vertically integrated foundry that uses particle accelerators to produce "the world's brightest beams, enabling a new method of advanced X-ray lithography." The company claims its technology is comparable to ASML's high NA EUV, and notes it can extend well beyond 2nm. ASML has not publicly commented. The Nexperia chip sho... » read more

Thermal, Mechanical, And Material Stresses Grow With Die Stacking
By Ann Mutschler - 30 Oct, 2025 - Comments: 0

Managing thermal and mechanical stress in multi-die assemblies will require a detailed knowledge of how and where a device will be used, how it will be packaged, and where stresses could cause problems at any point during its expected lifetime. This includes everything from workload-dependent thermal gradients to mechanical and electrical stress, which may become more pronounced over time wi... » read more

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