tag: Cadence

What Is 3D-IC Technology? Fundamentals, Architecture, And Design Concepts
By Reela Samuel - 25 Nov, 2025 - Comments: 0

As process nodes continue to advance into the sub-micron era, the limitations of traditional scaling are becoming increasingly evident. Larger monolithic chips are facing challenges such as higher power density, routing congestion, and reduced yield. Three-dimensional integrated circuits (3D-IC) technology represents a breakthrough approach by stacking multiple dies vertically. This design red... » read more

PCI Express Design Guide – Q&A for Gen 4, 5, 6
By Cadence - 24 Nov, 2025 - Comments: 0

High-speed PCB design for PCI Express Gen4, Gen5, and Gen6 pushes every dimension of signal integrity and layout engineering. This PCIe Design Guide – Q&A (Part 1) compiles 60 of the most common real-world design questions that engineers face—and provides detailed, practical answers grounded in simulation data, field experience, and compliance testing. Whether you’re defining your... » read more

Chip Industry Week In Review
By The SE Staff - 21 Nov, 2025 - Comments: 0

China's Hefei Lumiverse Technology reportedly has developed a desktop-sized High Harmonic Generation light source that generates wavelengths as small as 1nm. One customer already has used it to produce 14nm chips, which was the original target node for EUV, according to one report. As a point of comparison, TSMC and Samsung didn't start using EUV until the 7nm node, relying instead on immersion... » read more

Changes In Mixed-Signal IC Verification
By Ed Sperling - 19 Nov, 2025 - Comments: 0

Analog and digital engineers traditionally have worked in very different worlds. Many analog engineers for years have opted to verify analog designs by scrutinizing waveforms, while digital engineers have treated analog blocks like black boxes. But as these two areas converge in advanced SoCs and multi-die assemblies, the demarcation line between these engineering disciplines is being erased. S... » read more

The Future For Formal Verification
By Brian Bailey - 19 Nov, 2025 - Comments: 0

Experts at the table: Semiconductor Engineering sat down to discuss possible future directions for formal verification technology with Ashish Darbari, CEO for Axiomise; Jin Zhang, product management group director for the Verification Group at Cadence; Sean Safarpour, executive director for R&D at Synopsys; and Jeremy Levitt, principal engineer for Digital Verification Technology at Siemen... » read more

Blog Review: Nov. 19
By Jesse Allen - 19 Nov, 2025 - Comments: 0

Cadence's Mamta Rana explores how Forward Error Correction in PCIe 6.0 is key to its 64.0 GT/s per lane bandwidth by enabling the receiver to detect and correct errors without retransmissions or protocol-level recovery by adding redundant information to transmitted data. Siemens' Dave Rich shares a paper from DVCon 1992 that introduced a new RTL modeling construct to Verilog, eventually know... » read more

Chip Industry Week in Review
By The SE Staff - 14 Nov, 2025 - Comments: 0

Samsung reportedly is hiking memory chip prices by 30% to 60% due to high demand from AI data centers and constrained supplies. Those shortages are causing ripples elsewhere. SMIC, China's largest foundry, said its customers are holding back orders for other types of semiconductor due to concerns about memory supplies. Meanwhile, interest in photonics and power semiconductors is picking up, ... » read more

Noise: A Chip Killer
By Brian Bailey - 13 Nov, 2025 - Comments: 0

Noise has always been important to communications experts, but it's quickly becoming an issue that every semiconductor designer has to contend with. Some chips already have been compromised. Noise can be defined as any deviation from the ideal that can impact intended functionality. When it comes to semiconductors, that could mean the ability to reliably extract a signal value at the intende... » read more

Multiple AI Scale-Up Options Emerge
By Bryon Moyer - 13 Nov, 2025 - Comments: 0

Artificial intelligence (AI) workloads are very different from those traditionally run inside of data centers, and while the current infrastructure can accommodate those needs, there is a constant demand for higher performance and better power efficiency. It can take months to train a large language model, even with a huge number of processing elements. Typically this involves commandeering ... » read more

PCIe Low-Power Validation Challenges And Potential Solutions
By Kunal Chhabriya - 13 Nov, 2025 - Comments: 0

As chip complexities increase and the industry evolves to more battery-powered devices, power-aware/consumption research becomes an integral part of design in the industry. Low power is crucial in ASIC applications to ensure longevity, durability, and reliability. PCI-SIG has focused on reducing power consumption while the PCIe interface is active to enable better platform power management (... » read more

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