tag: Cadence

Blog Review: August 20
By Jesse Allen - 20 Aug, 2025 - Comments: 0

Cadence's Sriram Sharma Kalluri finds that time-of-flight sensors are poised to revolutionize ADAS by generating precise 3D point clouds that, particularly when combined with lidar, contribute to an exceptionally accurate and comprehensive understanding of the vehicle's surroundings. Synopsys' Igor Markov and other industry experts discuss how quantum computing is moving from research to p... » read more

Best Options For Using AI In Chip Design
By Ed Sperling - 20 Aug, 2025 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss how and where AI can be applied to chip design to maximize its value, and how that will impact the design process, with Chuck Alpert, Cadence Fellow; Sathish Balasubramanian, head of product marketing and senior director for custom IC at Siemens EDA; Anand Thiruvengadam, senior director and head of AI product management at S... » read more

Complex Mix Of Processors At The Edge
By Liz Allan - 18 Aug, 2025 - Comments: 1

With AI changing so fast, it’s a juggle for companies to ensure they can deliver the best performance now while also future-proofing for unknown AI models or a completely different approach to training and inference that may emerge. There are a slew of options for high-end and budget phones, hyperscalers, and low-cost, low-power edge devices, and while GPUs keep making headlines, many designe... » read more

Chip Industry Week in Review
By The SE Staff - 15 Aug, 2025 - Comments: 0

Lines are blurring between government and industry: On the heels of last week's resignation demand, Intel CEO Lip-Bu Tan met with President Trump on Monday, with the President later saying, "The meeting was a very interesting one. His success and rise is an amazing story."  Now, Bloomberg reports the Trump administration is in talks with Intel for the U.S. government to take a stake in th... » read more

Re-Architecting AI For Power
By Brian Bailey - 14 Aug, 2025 - Comments: 0

The industry is becoming increasingly concerned about the amount of power being consumed by AI, but there is no simple solution to the problem. It requires a deep understanding of the application, the software and hardware architectures at both the semiconductor and system levels, and how all of this is designed and implemented. Each piece plays a role in the total power consumed and the utilit... » read more

UEC-CBFC: Credit-Based Flow Control For Next-Gen Ethernet In AI And HPC
By Harinee Rathod - 14 Aug, 2025 - Comments: 0

For ages, Ethernet has been the backbone of networking — starting from simple web browsing to cloud computing, data centers, automobiles, and more. Ethernet has enabled countless innovations, and now, it's expanding to meet the demands of AI and HPC. As the world shifts toward these new technologies, new challenges are emerging. These include increased scale, higher bandwidth density, mult... » read more

Will New Processor Architectures Raise Energy Efficiency?
By Bryon Moyer - 14 Aug, 2025 - Comments: 1

Data centers continue to heat up as new processors consume more energy than ever before. Cooling is the primary weapon against the heat these processors generate, but it won’t be able to keep up forever with traditional processor architectures. New ones may be necessary. There are opportunities today to make well-known architectures more energy-efficient, but the number of options for subs... » read more

Time-of-Flight Decoding Enhanced By Tensilica Vision DSPs
By Cadence - 13 Aug, 2025 - Comments: 0

Time-of-Flight (ToF) technology has become a vital tool for precise depth perception in computer vision, driving innovation across diverse applications such as autonomous systems and medical equipment. Efficient processing of ToF data is paramount for realizing this technology’s full potential. This document highlights how Cadence's Tensilica Vision DSP architecture is significantly adv... » read more

What’s Different About HBM4
By Ed Sperling - 11 Aug, 2025 - Comments: 0

Memory bandwidth is limiting the flow of huge datasets that are needed to train AI models. There is much more data to process, store, and retrieve, but the speed at which that data moves through high-bandwidth memory (HBM) stacks is significantly lower than the speed at which data can be processed. Frank Ferro, group director for product management at Cadence, talks about the new HBM4 standard,... » read more

Chip Industry Week in Review
By The SE Staff - 08 Aug, 2025 - Comments: 1

Apple plans to increase its U.S. investment by an additional $100 billion over four years, which includes the launch of an advanced manufacturing supply chain program, spurring a number of related chip industry announcements, including: Apple will invest in Amkor's new packaging and test facility in Arizona as its first and largest customer, and Amkor will package and test Apple silicon pr... » read more

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