Scalable I/O Virtualization: A Deep Dive Into PCIe’s Next Gen Virtualization


The demands of modern cloud computing—massive scale, constant agility, and tight security—are pushing traditional I/O virtualization to its limits. While SR-IOV (Single Root I/O Virtualization) was a foundational technology, it wasn't built for the high-density, multi-tenant environments common today. To meet this challenge, the PCIe specification has evolved with Scalable I/O Virtualiza... » read more

AI Drives More Realistic Gaming


Video games are utilizing artificial intelligence to create increasingly realistic scenarios and interactions, enabled by big increases in processing horsepower and memory, and significantly faster data movement. GPUs, once confined to graphics rendering, are now also being deployed across a wide range of AI tasks, generating more realistic non-player characters, dynamic worlds, personalized... » read more

Agentic AI: Lots Of Little Black Boxes


AI is changing so quickly that it's not always clear how much of a security threat it poses for semiconductor design, and that uncertainty increases as AI agents are introduced into the mix. So far, the use of AI in chip design has been highly targeted. Most of what is included in design tools is some version of machine learning, bounded by tight control loops. EDA and IP vendors, large chip... » read more

SDVs And AI Forcing Big Changes In Automotive


The automotive industry is undergoing a fundamental transformation that includes everything from software-defined vehicles, the injection of AI into nearly every facet of the design and use case of a vehicle, and a complete overhaul of traditional relationships between different tiers and OEMs. The switch to software-defined vehicles is a top priority for the automotive ecosystem. It enables... » read more

Blog Review: Aug. 6


Cadence's Shyam Sharma checks out key features of the LPDDR6 specification, including data transfer speeds that can reach up to 14.4Gbps, two sub-channels per device, metadata built into the data packets, and row hammer mitigation. Synopsys' Frank Malloy and Vincent van der Leest describe the essential role that a hardware root of trust plays in providing a secure foundation for all other se... » read more

Chip Industry Week in Review


The U.S. government announced new import tariff actions and deals this week, including: The EU: 15% tariff on most goods including semiconductors. According to the EU's president, the action excludes semiconductor equipment. Copper: 50% tariff on all imports of semi-finished copper products and intensive copper derivative products, effective Aug. 1, but raw input material is excluded. ... » read more

UEC-LLR: The Future Of Loss Recovery In Ethernet For AI And HPC


As Artificial Intelligence (AI) and High-Performance Computing (HPC) systems become the backbone of modern data centers, they generate and consume a massive amount of data. Traditional Ethernet was not built for such high-bandwidth traffic. In HPCs and AI models, computations are distributed across the nodes and the data is shared in real time with low latency and lossless communication. As ... » read more

Multi-Modal AI In EDA Development Flows


RTL coding is a critical step in the development of semiconductors, but many would argue it is not the most difficult. Things become a lot more complex as you get closer to implementation, and as the system context becomes larger than can be comprehended by text alone. In both cases, layout, timing, power, and many other factors come into play, but none is as easily represented by text, and the... » read more

How AI Will Impact Chip Design And Designers


Experts at the Table: Semiconductor Engineering sat down to discuss the role and impact of AI in chip design with Chuck Alpert, Cadence Fellow; Sathish Balasubramanian, head of product marketing and senior director for custom IC at Siemens EDA; Anand Thiruvengadam, senior director and head of AI product management at Synopsys; Sailesh Kumar, CEO of Baya Systems; Mehir Arora, head of engineering... » read more

Streamlining Functional Verification For Multi-Die And Chiplet Designs


An Opportunity and a Challenge The manufacturing aspects of multi-die/multi-chiplet designs are often highlighted, but what about verification? Functional correctness and performance of inter-die connections via a standard interface, such as UCIe or a custom inter-die interface, are not guaranteed to meet all system requirements. These interfaces must be verified comprehensively, ensuring co... » read more

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