tag: Cadence

IP Integration Challenges Increase
By Ed Sperling - 08 Jul, 2015 - Comments: 0

Semiconductor Engineering sat down with Chris Rowen, CTO of [getentity id="22032" e_name="Cadence"]'s IP group; Rob Aitken, an [getentity id="22186" comment="ARM"] fellow; Patrick Soheili, vice president of product management and corporate development at [getentity id="22242" e_name="eSilicon"]; Navraj Nandra, senior director of marketing for DesignWare analog and mixed-signal IP at [getentity ... » read more

Blog Review: July 8
By Jesse Allen - 08 Jul, 2015 - Comments: 0

In this week's picks for his top five technology articles, Ansys' Justin Nescott rolls in with two ways for cyclists to improve safety, the development of the wheelchair and the advancement of fingerprint scanners for healthcare and security. With the launch of the BBC Micro:bit, one part of a program to inspire young people to get into coding and digital creation, ARM's Gary Atkinson shows ... » read more

Formal Verification For Post-Silicon Debug
By Cadence - 08 Jul, 2015 - Comments: 0

Bug escape costs grow considerably with each and every subsequent step in the design flow, to the point of being exorbitantly high once at the silicon level. As a result, these high costs of bug escape are driving customers to embrace formal verification for post-silicon debug and to begin using formal far earlier in the flow for their next design projects. The Cadence JasperGold Verification S... » read more

How Much Security Is Enough?
By Ed Sperling - 06 Jul, 2015 - Comments: 3

Semiconductor Engineering sat down to discuss the current state of [getkc id="223" kc_name="security"] and what must be done in the future, with Denis Noël, head of cyber security solutions at [getentity id="22499" e_name="NXP"]; Serge Leef, vice president of new ventures at [getentity id="22017" e_name="Mentor Graphics"]; Andreas Kuehlman, senior vice president and general manager of the soft... » read more

Blog Review: July 1
By Jesse Allen - 01 Jul, 2015 - Comments: 0

On the eve of his retirement, Cadence's Richard Goering takes a look back at 30 years of covering EDA: the highlights, the lowlights, and the headlights shining into the future. Established nodes are experiencing a much higher demand than one might normally expect at this point in their lifecycle. Mentor's Michael White examines the dynamics and market forces behind the longevity, and the ch... » read more

The Week In Review: Manufacturing
By Mark LaPedus - 26 Jun, 2015 - Comments: 0

Semiconductor Manufacturing International Corp. (SMIC), Huawei, Imec and Qualcomm have announced the formation of the SMIC Advanced Technology Research & Development (Shanghai) Corp., an equity joint venture company. Located in China, the joint venture company will focus on R&D towards next-generation CMOS logic technology. The current focus will be on developing 14nm logic technology, ... » read more

More Data, Different Approaches
By Ed Sperling - 25 Jun, 2015 - Comments: 0

Scaling, rising complexity, and integration are all contributing to an explosion in data, from initial design to physical layout to verification and into the manufacturing phase. Now the question is what to do with all of that data. For SoC designs, that data is critical for identifying real and potential problems. It also allows verification engineers working the back end of the design flow... » read more

EDA’s Clouded Future
By Brian Bailey - 25 Jun, 2015 - Comments: 0

There was a time, not that long ago, when chip design and EDA tools consumed some of the largest data centers with tens of thousands of machines and single datasets that consumed more than a hard disk could hold. The existing IT capabilities of the times were stretched to their limits. But while design sizes grew, other aspects of the flow did not develop as fast. “This has been driven by ... » read more

What Is A System Now?
By Ann Mutschler - 25 Jun, 2015 - Comments: 0

Defining a system used to be relatively straightforward. But as systems move onto chips, and as those chips increasingly are connected with applications and security spanning multiple devices, the definition is changing. This increases the complexity of the design process itself, and it raises questions about how chips and software will be designed and defined in the age of the [getkc id="76... » read more

Towards A Metric To Measure Verification Computing Efficiency
By Frank Schirrmeister - 25 Jun, 2015 - Comments: 1

Thinking back about DAC 2015 in San Francisco earlier this month, I am happy that at least some of my predictions came true—there was clearly a trend towards making verification smarter. However, one thing struck me while hearing all the discussions on connecting engines is what Jim Hogan called the continuum of verification engines (COVE)—and what we at Cadence call the system development ... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy