tag: Cadence

System Design Enabling Surround Computing
By Frank Schirrmeister - 23 Oct, 2014 - Comments: 0

For a while now I have been wondering about the next killer application driving electronics. During CDNLive in Austin a couple of weeks ago, Dr. Lisa Su, at the time still Chief Operating Officer and since October 7th president and CEO at AMD, gave some answers at a keynote titled, “The Trends Redefining Our Industry.” The answer may well be “surround computing.” Su identified a coup... » read more

Top 10 Ways To Automate Verification
By Cadence - 22 Oct, 2014 - Comments: 0

It’s a persistent theme: engineers are expected to do more with the same or fewer resources. Meantime, designs continue to grow larger and more complex. Studies have shown that verification continues to consume up to 70% of the IC development cost in each advanced node. Cadence’s R&D teams designed the latest version of the Incisive® functional verification platform with these pressures in... » read more

Blog Review: Oct. 22
By Ed Sperling - 22 Oct, 2014 - Comments: 0

What is UX? The User Experience, of course. Rambus' Aharon Etengoff notes that the IoT UX is now the subject of a Harvard Business Review article. A long list of hurdles are expected at the 10nm process node, including multiple levels of local interconnects, more complex layout rules, timing problems, and a slew of others. Cadence's Richard Goering puts it all in perspective. Mentor's R... » read more

Securing The IoT
By Ed Sperling - 20 Oct, 2014 - Comments: 1

Semiconductor Engineering sat down to discuss whether the [getkc id="76" comment="Internet of Things"] will be secure enough, or whether it will create new security issues, with Sami Nassar, general manager of [getentity id="22499" comment="NXP Semiconductor"]; Oleg Logvinov, director for special assignments at [getentity id="22331" comment="STMicroelectronics"]; and Lawrence Loh, application e... » read more

Memory Directions Uncertain
By Brian Bailey - 17 Oct, 2014 - Comments: 0

Semiconductor Engineering sat down with a panel of experts to find out what is happening in world of memories. Taking part in the discussion are [getperson id="11073" comment="Charlie Cheng"], chief executive officer at [getentity id="22135" e_name="Kilopass Technology"]; Navraj Nandra, senior director of marketing for Analog/Mixed signal IP, embedded memories and logic libraries at [getentity ... » read more

Week 19: Ready. Steady. Go!
By Anne Cirkel - 17 Oct, 2014 - Comments: 2

The window for submitting to the IP and designer tracks opens on Oct. 23. It’s time to get ready and check with your management if you can present your work at DAC. You can find the submission details and a link to last year’s content here. You can even browse presentation examples from past designer tracks. If you are an EDA vendor, the designer track is a good opportunity for your use... » read more

The Week In Review: Design
By Ed Sperling - 17 Oct, 2014 - Comments: 0

Legal Mentor Graphics won a $36 million award plus royalties stemming from a patent infringement case involving EVE (Emulation & Verification Engineering), an emulation company that was purchased by Synopsys in 2012. A U.S. District Court jury in the District of Oregon found that EVE had directly and indirectly infringed on a 2001 patent entitled "Method and apparatus for gate-level simula... » read more

Blog Review: Oct. 15
By Ed Sperling - 15 Oct, 2014 - Comments: 0

Obesity makes your liver age faster, but you'll need a sophisticated biological clock to see that. Ansys' Bill Vandermark uncovers the top 5 engineering articles of the week. This one includes cyborg horses and an implanted prosthetic arm. Mentor's Colin Walls takes a look at "hard" and "soft" real time. It sounds like something out of a Salvador Dali painting. Rambus' Aharon Etengoff t... » read more

High-Level Gaps Emerge
By Ann Mutschler - 15 Oct, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss the attributes of a high-level, front-end design flow with Bernard Murphy, CTO at [getentity id="22026" e_name="Atrenta"]; Leah Clark, associate technical director for digital video technology at Broadcom; Phil Bishop, vice president of the system level design system & verification group at [getentity id="22032" e_name="Cadence"]; and Jon McDon... » read more

Will There Be A DDR5?
By Ed Sperling - 10 Oct, 2014 - Comments: 1

DDR4 rollouts have begun. And in the DRAM world that begs the question, 'What comes next?' The answer isn't so obvious. While there have been suggestions inside of JEDEC — the Joint Electron Device Engineering Council, which has overseen the standards for double-data-rate synchronous DRAM — to develop a DDR5 standard, it's not the only solution being considered. And in the minds of some... » read more

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