tag: Cadence

Shifts In Verification
By Ed Sperling - 25 Apr, 2013 - Comments: 0

By Ann Steffora Mutschler Verifying an SoC requires a holistic view of the system, and engineering teams use a number of tools to reach a high degree of confidence in the coverage. But how and when to use those tools is in flux as engineering teams wrestle with increasing complexity at every level of the design, and a skyrocketing increase in the challenge of verifying it. There are no ... » read more

Beyond Software: The Virtual-Machine Supply System
By The SE Staff - 25 Apr, 2013 - Comments: 0

It’s no secret that EDA and IP companies have had to expand their coverage into the larger system market, thanks to changes in the semiconductor supply chain. Around 2000, the industry was very fragmented. Mobile-chip and IP vendors worked with handset makers, who then partnered with operating-system (OS) suppliers and finally network operators. The next 12 years resulted in various combinati... » read more

Taking Aim At Big Data
By Ed Sperling - 25 Apr, 2013 - Comments: 0

By Ed Sperling As the Internet of Things bridges the gap between the mobile and big data worlds, EDA and IP vendors increasingly are looking well beyond their usual boundaries. How successful they are at moving upward into a market that is far less price-sensitive remains to be seen. But from a technology standpoint, at least, the issues encountered by data centers and cloud providers are ... » read more

Experts At The Table: The Internet Of Everything
By Ed Sperling - 25 Apr, 2013 - Comments: 0

By Ed Sperling System-Level Design sat down to discuss the Internet of Things with Jack Guedj, president and CEO of Tensilica; John Heinlein, vice president of marketing for the physical IP division of ARM; Kamran Izadi, director of sourcing and supplier management at Cisco; and Oleg Logvinov, director of market development for STMicroelectronics’ Industrial and Power Conversion Division. Wh... » read more

Using Power Aware IBIS v5.0 Behavioral IO Models To Simulate Simultaneous Switching Noise
By Various Writers - 25 Apr, 2013 - Comments: 0

Typically simultaneous switching noise (SSN) transient simulations require significant CPU and RAM resources. A prominent factor affecting both CPU and RAM resource requirements is the number of MOSFET models included in the post layout extracted IO netlists. By replacing the IO netlists with power aware IBIS v5.0 behavioral models, both the CPU and RAM resource requirements are dramatically re... » read more

Subsystems And Reuse
By Frank Schirrmeister - 23 Apr, 2013 - Comments: 0

By Frank Schirrmeister The last couple of weeks have been very busy with travel, customer meetings and presentations—DATE in Grenoble, CDNLive in San Jose and, most recently, EDPS in Monterey. Software enablement and IP sub-systems have been the key themes throughout these events, and during Gary Smith’s keynote at EDPS, I realized that subsystem reuse may be a significant step to solving ... » read more

Experts At The Table: FinFET Questions And Issues
By Ed Sperling - 19 Apr, 2013 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss the current state and future promise of finFETs, and the myriad challenges, with Ruggero Castagnetti, an LSI fellow; Barry Pangrle, senior power methodology engineer at Nvidia; Steve Carlson, group director of marketing at Cadence; and Mary Ann White, director of product marketing at Synopsys. What follows are excerpts o... » read more

Design-For-DSA Industry Begins To Assemble
By Mark LaPedus - 18 Apr, 2013 - Comments: 0

By Mark LaPedus The industry is aggressively pursuing directed self-assembly (DSA) as an alternative patterning technology for future chip designs. DSA, which enables fine pitches through the use of block copolymers, is in the R&D pilot line stage today. The fab tools, process flows and materials are basically ready, but there are still several challenges to bring the technology from th... » read more

Fixing DP Errors: Colors Or Rings
By Ann Mutschler - 18 Apr, 2013 - Comments: 0

By Ann Steffora Mutschler With the move to the 20nm manufacturing node, double patterning (DP) became a requirement. In addition, topology changes occurred that demanded very regular structures, marking a significant departure from 28nm design. As a result of this new approach, new errors are popping up, such as DP violation loops, odd cycle violations and anchor path violations. Certain... » read more

Dangerous Electricity
By Ann Mutschler - 11 Apr, 2013 - Comments: 0

Electricity to the modern age is as indispensible as air, but too much can be a bad thing for automotive and aerospace applications—especially when it is in the form of electrostatic discharge (ESD). As chips advance to 28nm, 20nm and 16nm, the design window for electrostatic discharge is shrinking for a number of reasons, explained Norman Chang is vice president and senior product strategis... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy