tag: Cadence

Keeping Pace With Moore’s Law
By Ann Mutschler - 19 Dec, 2012 - Comments: 0

By Ann Steffora Mutschler As the number of transistors doubles with each move to a smaller manufacturing process technology, there are questions as to whether the current cadre of place and route tools will be able to keep in lock step. Have no fear, assured Saleem Haider, senior director of marketing for physical design and DFM at Synopsys. “For the increase in densities that we get with... » read more

TLM-Driven Design And Verification—Time For A Methodology Shift
By Various Writers - 19 Dec, 2012 - Comments: 0

While today’s RTL design and verification flows are a step up from the gate-level flows of two decades ago, RTL flows are straining to meet the demands of most product teams. When designs are sourced and verified at the register transfer level (RTL), IP reuse is difficult, functional verification is lengthy and cumbersome, and architectural decisions cannot be confirmed prior to RTL verificat... » read more

Looking Back At 2012
By Frank Schirrmeister - 17 Dec, 2012 - Comments: 1

By Frank Schirrmeister This my last post in this Blog for this year and it is time to look back at the year and try to see what’s next. How fast time flies became clear in a funny way to me this morning when listening to the “Tagesschau” while showering – the 8pm news I grew up with back in Germany – courtesy of modern video Blog technology. Apparently the parking fines in inner citi... » read more

Experts At The Table: SoC Verification
By Ed Sperling - 14 Dec, 2012 - Comments: 0

By Ed Sperling System-Level Design sat down to discuss the challenges of verification with Frank Schirrmeister, group director for product marketing of the System Development Suite at Cadence; Charles Janac, chairman and CEO of Arteris, Venkat Iyer, CTO of Uniquify; and Adnan Hamid, CEO of Breker Verification Systems. What follows are excerpts of that discussion. SLD: How important is it t... » read more

DFM Challenges Abound Below 20nm
By Ed Sperling - 13 Dec, 2012 - Comments: 0

By Ann Steffora Mutschler As semiconductor design teams struggle to wring the last few percentage of die shrink from a technology node, much of the ability to do that rests on the EDA tools. From place and route through DFM checks—essentially, everything that happens before the design is sent to the fab or foundry—it all must be tightly integrated with the manufacturing process so it co... » read more

Experts At The Table: Obstacles In Low-Power Design
By Ed Sperling - 06 Dec, 2012 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss low-power design with with Leah Clark, associate technical director at Broadcom; Richard Trihy, director of design enablement at GlobalFoundries; Venki Venkatesh, engineering director at Atrenta; and Qi Wang, technical marketing group director at Cadence. What follows are excerpts of that conversation. LPHP: If you ar... » read more

Tech Talk: LP Design And Verification
By Ed Sperling - 06 Dec, 2012 - Comments: 0

Cadence's Qi Wang talks with Low-Power/High-Performance Engineering about power formats and what else can be done to save power in SoCs. [youtube vid=afJ6VQ0AYgg] » read more

Experts At The Table: Obstacles In Low-Power Design
By Ed Sperling - 06 Dec, 2012 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss low-power design with with Leah Clark, associate technical director at Broadcom; Richard Trihy, director of design enablement at GlobalFoundries; Venki Venkatesh, engineering director at Atrenta; and Qi Wang, technical marketing group director at Cadence. What follows are excerpts of that conversation. LPHP: If you ar... » read more

Experts At The Table: SoC Verification
By Ed Sperling - 29 Nov, 2012 - Comments: 0

By Ed Sperling System-Level Design sat down to discuss the challenges of verification with Frank Schirrmeister, group director for product marketing of the System Development Suite at Cadence; Charles Janac, chairman and CEO of Arteris, Venkat Iyer, CTO of Uniquify; and Adnan Hamid, CEO of Breker Verification Systems. What follows are excerpts of that discussion. SLD: As we get more third-... » read more

Taming The Challenges Of 20nm Custom/Analog Design
By Various Writers - 29 Nov, 2012 - Comments: 0

Custom and analog designers will lay the foundation for 20nm IC design. However, they face many challenges that arise from manufacturing complexity. The solution lies not just in improving individual tools, but in a new design methodology that allows rapid layout prototyping, in-design signoff, and close collaboration between schematic and layout designers. To view this white paper, click here. » read more

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