tag: Cadence

The Agony Of Choice
By Frank Schirrmeister - 28 Nov, 2012 - Comments: 0

By Frank Schirrmeister In my last post on “The Complexity of System Development and Verification” I outlined five main use models for verification at four levels of scope, enabled by seven execution engines. So how exactly do users choose between the different execution engines to run hardware and software together before the actual chip is available? It is far from trivial. The seven engi... » read more

The Growing Verification Challenge
By Ed Sperling - 28 Nov, 2012 - Comments: 0

System-Level Design talks with Charles Janac of Arteris, Frank Schirrmeister of Cadence, Venkat Iyer of Uniquify and Adnan Hamid of Breker Verification Systems about the growing difficulty of verifying complex SoCs and what lies ahead. [youtube vid=zUB4_t9teE8] » read more

Experts At The Table: Obstacles In Low-Power Design
By Ed Sperling - 16 Nov, 2012 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss low-power design with with Leah Clark, associate technical director at Broadcom; Richard Trihy, director of design enablement at GlobalFoundries; Venki Venkatesh, engineering director at Atrenta; and Qi Wang, technical marketing group director at Cadence. What follows are excerpts of that conversation. LPHP: What effe... » read more

Spoiled By Moore’s Law
By Ed Sperling - 08 Nov, 2012 - Comments: 0

By Ann Steffora Mutschler Over the past 20 years, lithium ion has emerged as the predominant battery technology. While there are a few variants, it seems that for everything from smartphones to automobiles, the same basic technology is being used. Many other technologies that have come and gone over the years—nickel cadmium, nickel metal hydride come to mind in the recent past, but they ar... » read more

More Art Than Science
By Ed Sperling - 08 Nov, 2012 - Comments: 0

By Ann Steffora Mutschler Not so long ago, high-end digital devices were mostly just digital. Today large SoCs contain a significant amount of analog/mixed-signal content. And given that analog circuits have certain sensitivities different from digital blocks, there is a desire to convert some of those analog signals to digital to achieve power savings and take advantage of digital verificat... » read more

The Growing Integration Challenge
By Ed Sperling - 08 Nov, 2012 - Comments: 0

By Ed Sperling As the number of processors and the amount of memory and IP on a chip continues to skyrocket, so does the challenge for integrating all of this stuff on a single die—or even multiple dies in the same package. There are a number of reasons why it’s getting more difficult to make all of these IP blocks work together. First of all, nothing ever stands still in design. As a r... » read more

Power Impacts On Advanced Node IP
By Ed Sperling - 08 Nov, 2012 - Comments: 0

By Ann Steffora Mutschler With the move to the 28nm or 20nm process nodes, SoC engineering teams are seeing a significant amount of variations due to manufacturability. To reflect how a design element will be printed on the wafer, foundries offer many libraries with multiple corners for different voltages, timing and temperature, among other things. “At 28nm what we are seeing is a l... » read more

CPF 2.0 Voltage Regulator And Analog Ports
By Luke Lang - 08 Nov, 2012 - Comments: 0

By Luke Lang CPF 2.0 was released more than a year and half ago, yet the majority of the designs are still done with CPF 1.1. This is one of those good news/bad news situations. The good news is that CPF 1.1 is perfectly adequate for majority of the LP designs. The bad news is that designers may not be aware of the new CPF 2.0 features that could be quite useful. This month, we will take a loo... » read more

Roundtable: Lower-Power Chips
By Ed Sperling - 08 Nov, 2012 - Comments: 0

Low Power-High Performance Engineering talks about problems in low-power design with Richard Trihy of GlobalFoundries, Leah Clark of Broadcom, Qi Wang of Cadence and Venki Venkatesh of Atrenta. [youtube vid=cD560pgEegk] » read more

Experts At The Table: Obstacles In Low-Power Design
By Ed Sperling - 08 Nov, 2012 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss low-power design with with Leah Clark, associate technical director at Broadcom; Richard Trihy, director of design enablement at GlobalFoundries; Venki Venkatesh, engineering director at Atrenta; and Qi Wang, technical marketing group director at Cadence. What follows are excerpts of that conversation. LPHP: What are ... » read more

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