tag: Codasip

What Worked, What Didn’t In 2019
By Brian Bailey - 19 Dec, 2019 - Comments: 1

2019 has been a tough year for semiconductor companies from a revenue standpoint, especially for memory companies. On the other hand, the EDA industry has seen another robust growth year. A significant portion of this disparity can be attributed to the number of emerging technology areas for semiconductors, none of which has reached volume production yet. Some markets continue to struggle, a... » read more

Week In Review: Design, Low Power
By Jesse Allen - 13 Dec, 2019 - Comments: 0

Rambus finalized its acquisition of the silicon IP, secure protocols and provisioning business from Verimatrix, formerly Inside Secure, for $45 million at closing, and up to an additional $20 million, subject to certain revenue targets in 2020. RISC-V SiFive unveiled two new product families. The SiFive Apex processor cores target mission-critical processors with Size, Weight, and Power (SW... » read more

Week in Review: IoT, Security and Automotive
By SE Staff - 13 Dec, 2019 - Comments: 0

Internet of Things Western Digital Corp. and Codasip are working together on Western Digital’s SweRV Core EH1, which is a RISC-V core with a 32-bit, dual superscalar, 9-stage pipeline architecture. The core, launched earlier this is aimed at embedded devices supporting data-intensive edge applications, such as storage controllers, industrial IoT, real-time analytics in surveillance systems, ... » read more

RISC-V Markets, Security And Growth Prospects
By Ed Sperling - 18 Nov, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss open instruction set hardware with Ben Levine, senior director of product management in Rambus' Security Division; Jerry Ardizzone, vice president of worldwide sales at Codasip; Megan Wachs, vice president of engineering at SiFive; and Rishiyur Nikhil, CTO of Bluespec. What follows are excerpts of that conversation.  Part one of this discussion is ... » read more

RISC-V Challenges And Opportunities
By Ed Sperling - 24 Oct, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss open instruction set hardware and the future of RISC-V with Ben Levine, senior director of product management in Rambus' Security Division; Jerry Ardizzone, vice president of worldwide sales at Codasip; Megan Wachs, vice president of engineering at SiFive; and Rishiyur Nikhil, CTO of Bluespec. What follows are excerpts of that conversation. (L-... » read more

Open ISAs Gaining Traction
By Ann Mutschler - 26 Sep, 2019 - Comments: 0

Open instruction set architectures are starting to gain a foothold, often in combination with other processors, as chipmakers begin to add more specialized compute elements and more flexibility into their designs. There are a number of these open ISAs available today, including Power, MIPS, and RISC-V, and there are a number of permutations and tools available for sale based on those archite... » read more

Better Benchmarks Through Compiler Optimizations: Codasip Jump Threading
By Codasip - 25 Sep, 2019 - Comments: 0

The architectural efficiency of embedded processor IP is measured by a small set of industry standard benchmarks, that even though often bear little correlation to real workloads, continue to persist. The most popular benchmarks are Dhrystone and CoreMark. An interesting observation regarding these test suites is that the performance numbers continue to improve for a given architecture, even... » read more

Trading Off Power And Performance Earlier In Designs
By Ann Mutschler - 12 Sep, 2019 - Comments: 0

Optimizing performance, power and reliability in consumer electronics is an engineering feat that involves a series of tradeoffs based on gathering as much data about the use cases in which a design will operate. Approaches vary widely by market, by domain expertise, and by the established methodologies and perspective of the design teams. As a result, one team may opt for a leading-edge des... » read more

Week In Review: Design, Low Power
By Jesse Allen - 30 Aug, 2019 - Comments: 0

Rambus completed its acquisition of Northwest Logic, a supplier of memory, PCIe and MIPI digital controllers. The Hillsboro, OR office of Northwest Logic will remain in place, along with the entire staff. SureCore launched a new low power design service. The company's offering includes concept-to-tape-out low power mixed-signal design expertise such as design and layout capabilities, technol... » read more

Week In Review: Design, Low Power
By Jesse Allen - 23 Aug, 2019 - Comments: 0

Xilinx debuted the Virtex UltraScale+ VU19P, which the company says is now the world's largest FPGA at 1.6X the size of its predecessor. The VU19P features 35 billion transistors, 9 million system logic cells, up to 1.5 terabits per-second of DDR4 memory bandwidth and up to 4.5 terabits per-second of transceiver bandwidth, and over 2,000 user I/Os. With a set of debug, visibility tools, and IP,... » read more

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