tag: Codasip

Blog Review: June 21
By Jesse Allen - 21 Jun, 2023 - Comments: 0

Synopsys' Vikram Bhatia identifies four trends driving the migration of EDA tools and chip design workloads to the cloud, from ever-increasing compute and time-to-market demands to advanced cybersecurity features. Cadence's Veena Parthan checks out how computational fluid dynamics and finite element analysis can help improve aquaculture with sustainable fish cage nets that minimize stagnatio... » read more

L31 Embedded Core Extensions For Wireless And Connectivity
By Codasip - 21 Jun, 2023 - Comments: 0

5G is the latest generation of cellular networks using the 3rd Generation Partnership Project (3GPP) 5G New Radio air interface. Unlike previous generations of network (2G, 3G & 4G), which had a one-size-fits-all approach, 5G aims to address a wide range of very different applications. To flexibly support diverse quality of service requirements, network slicing is introduced to enable multip... » read more

Power/Performance Costs Of Securing Systems
By Brian Bailey - 08 Jun, 2023 - Comments: 0

For much of the chip industry, concerns about security are relatively new, but the requirement for protecting semiconductor devices is becoming pervasive. Unfortunately for many industries, that lesson has been learned the hard way. Security breaches have led to the loss of sensitive data, ransomware attacks that lock up data, theft of intellectual property or financial resources, and loss o... » read more

Software-Defined Hardware Architectures
By Brian Bailey - 31 May, 2023 - Comments: 0

Hardware/software co-design has been a goal for several decades, but success has been limited. More recently, progress has been made in optimizing a processor as well as the addition of accelerators for a given software workload. While those two techniques can produce incredible gains, it is not enough. With increasing demands being placed on all types of processing, single-processor solutio... » read more

IP Becoming More Complex, More Costly
By Brian Bailey - 25 May, 2023 - Comments: 0

Success in the semiconductor intellectual property (IP) market requires more than a good bit of RTL. New advances mandate a complete design, implementation, and verification team, which limits the number of companies competing in this market. What constitutes an IP block has changed significantly since the concept was first introduced in the 1990s. What was initially just a piece of RTL (reg... » read more

No One-Size-Fits-All Approach To RISC-V Processor Optimization
By Mike Eftimakis - 25 May, 2023 - Comments: 0

As the demand for high-performance processors continues to grow and semiconductor scaling laws continue to show their limits, the need for processor optimization is inevitable. As I explained in a previous blog, RISC-V is designed to enable this. However, there is no one-size-fits-all approach to processor optimization. As each workload and each application will have their own requirements, th... » read more

A Formal-Based Approach For Efficient RISC-V Processor Verification
By Codasip - 24 May, 2023 - Comments: 0

The openness of RISC-V allows customizing and extending the architecture and microarchitecture of a RISC-V based core to meet specific requirements. This appetite for more design freedom is also shifting the verification responsibility to a growing community of developers. Processor verification, however, is never easy. The very novelty and flexibility of the new specification results in new fu... » read more

Blog Review: May 24
By Jesse Allen - 24 May, 2023 - Comments: 0

Siemens' Patrick McGoff finds that designers have not had easy tools to address solderability, leaving a critical part of the manufacturing success of a PCB to the component engineer or the contract manufacturer, and points to manufacturing-driven design as a way to avoid quality issues later. Cadence's Rich Chang finds that effective UPF low-power verification and debug involves more than o... » read more

Blog Review: May 10
By Jesse Allen - 10 May, 2023 - Comments: 0

Synopsys' Alessandra Nardi and Uyen Tran explain how to meet quality, reliability, functional safety, and security requirements of automotive chips through thorough test programs, path-margin monitoring, and design failure mode and effect analysis (DFMEA). Cadence's Veena Parthan explores how computational fluid dynamics can help predict and model the generation, propagation, and mitigation ... » read more

Working With The NimbleAI Project To Push The Boundaries Of Neuromorphic Vision
By Tora Fridholm - 27 Apr, 2023 - Comments: 0

At the end of 2022, the EU kicked off a cool project that aims to implement neuromorphic vision. But what is that? Let’s take a deeper look at the project and our contribution. First, if you are not familiar with Codasip Labs, I want to mention this briefly. Codasip Labs is in fact our innovation hub where we explore new technologies and try to contribute to the technology of the future. ... » read more

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