tag: EDA

Can EDA Keep Growing?
By Ed Sperling - 26 Jun, 2014 - Comments: 0

Slower progress at the leading edge of process technology, coupled with rising costs and fewer design starts, are changing the economics of the EDA world. Not surprisingly, there is almost a direct correlation between the shrinking number of startups in the field and the number of customers working on the most advanced nodes. So what exactly does this mean for the EDA world? Big changes, for... » read more

Without Moore’s Law: EDA
By Brian Bailey - 26 Jun, 2014 - Comments: 3

Semiconductor Engineering is examining the assertion about the end of Moore’s Law in a number of different ways. The special report, “Will 7nm and 5nm really happen?” looked at the technical aspects related to continuing into finer geometries. “Moore’s Law Tail No Longer Wagging the Dog” asked the question about the economics of people being able to afford to go to the latest node. ... » read more

Blog Review: June 4
By Ed Sperling - 04 Jun, 2014 - Comments: 0

Sonics' Drew Wingard looks at the challenges of IP integration, from standards to re-use to the need for intelligence on the network. Given the focus on IP integration, as well as the myriad challenges, this is very timely information. ARM's Karthik Ranjan has an interesting theory about why Java developers wear glasses. Ansys' Justin Nescott unearths the five most interesting engineering... » read more

Executive Insight: Aart de Geus
By Ed Sperling - 02 Jun, 2014 - Comments: 0

SE: What worries you most? De Geus: Everything I do is with high intensity, and what is of super high intensity right now—and there are challenges and opportunities in it—is that we have the confluence of some very big changes right now happening at the same time. On the technology side, there are multiple intersections. One is the intersection of another 10 years of Moore’s Law—finF... » read more

Easing The Path To Evolution
By Ann Mutschler - 29 May, 2014 - Comments: 1

On the surface, revolutionary changes in EDA seem unlikely due to the risk of replacing costly tools, flows and methodologies. But are they really? The answer depends on whom you ask. For Part One, click here. Risk is a big part of the equation here. “There are always pioneers in an organization and what you need to do is find someone who is willing to take some risk and typically it’s o... » read more

Executive Insight: Prakash Narain
By Ed Sperling - 27 May, 2014 - Comments: 0

SE: What’s your biggest concern? Narain: We are a smaller company, and ultimately we compete on the basis of the quality of the solutions we provide to customers. What’s the value proposition? How many X better will our solution be compared to the existing solutions that are in deployed in the market? You make a projection about it in your mind, and you make investments, and until they�... » read more

EDA Economics Changing
By Ed Sperling - 22 May, 2014 - Comments: 0

From most perspectives, there has never been a better time to be in the EDA business. Automation tools are in demand as complexity rises, and new companies jumping into the semiconductor business are starting out with commercially available tools rather than developing their own—and taking years, sometimes even decades, to replace them. EDA’s slice of the semiconductor market consistent... » read more

The Circle Of Test And EDA Is Complete
By Brian Bailey - 22 May, 2014 - Comments: 1

For those of you who were around and involved with EDA back in the early ’80s, you may remember that chip design was not the focus. It was the board that received most of the attention. Chips were small and did not require much in the way of functional verification. [getkc id="29" kc_name="Synthesis"] had not been invented and so gate-level design was where everything happened, and much of th... » read more

EDA Races To 7nm, Despite Litho Uncertainties
By Ann Mutschler - 16 May, 2014 - Comments: 0

It’s becoming almost painful to refer to the delay with EUV, but it certainly isn’t stopping anyone on the design side from tweaking design tools or working on test chips. Clearly, things are moving ahead to 7nm even though lithography plans aren't yet clear. Steve Carlson, group marketing director in Cadence’s Office of Chief Strategy, said with regard to EUV, “They have the power p... » read more

How Much Testing Is Enough?
By Mark LaPedus - 15 May, 2014 - Comments: 1

As chipmakers move towards finer geometries, IC designs are obviously becoming more complex and expensive. Given the enormous risks involved, chipmakers must ensure the quality of the parts before they go out the door. And as part of quality assurance process, that requires a sound test strategy. But for years, IC makers have faced the same dilemma. On one hand, they want a stringent test me... » read more

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