tag: EDA

The Circle Of Test And EDA Is Complete
By Brian Bailey - 22 May, 2014 - Comments: 1

For those of you who were around and involved with EDA back in the early ’80s, you may remember that chip design was not the focus. It was the board that received most of the attention. Chips were small and did not require much in the way of functional verification. [getkc id="29" kc_name="Synthesis"] had not been invented and so gate-level design was where everything happened, and much of th... » read more

EDA Races To 7nm, Despite Litho Uncertainties
By Ann Mutschler - 16 May, 2014 - Comments: 0

It’s becoming almost painful to refer to the delay with EUV, but it certainly isn’t stopping anyone on the design side from tweaking design tools or working on test chips. Clearly, things are moving ahead to 7nm even though lithography plans aren't yet clear. Steve Carlson, group marketing director in Cadence’s Office of Chief Strategy, said with regard to EUV, “They have the power p... » read more

How Much Testing Is Enough?
By Mark LaPedus - 15 May, 2014 - Comments: 1

As chipmakers move towards finer geometries, IC designs are obviously becoming more complex and expensive. Given the enormous risks involved, chipmakers must ensure the quality of the parts before they go out the door. And as part of quality assurance process, that requires a sound test strategy. But for years, IC makers have faced the same dilemma. On one hand, they want a stringent test me... » read more

FinFET Learning
By Ed Sperling - 08 May, 2014 - Comments: 0

FinFETs are not simple to work with. They’re difficult to manufacture, tricky to design, and they run the risk of greatly increased dynamic power density—particularly at 14/16nm, where extra margin is hard to justify—which affects everything from electromigration to signal integrity. Moreover, while finFETs have been on the drawing board for more than a decade, it’s taken four years ... » read more

Productive Clock Domain Crossing Verification
By Kiran Vittal - 08 May, 2014 - Comments: 2

Recently, we were invited to participate in an internal Chips@Cisco event along with other EDA vendors and FPGA providers. Executives from these vendors participated in a panel to discuss the challenges seen by the technology leaders in FPGAs and what it means to the industry. Everyone on the panel agreed that design size and complexity, including clock domains, is continuing to follow Moore’... » read more

Low-Power SoC Design
By Anand Iyer - 08 May, 2014 - Comments: 1

Over the last decade, power has become the primary design constraint for all SoC designs. While power reduction started in mobile market segments due to the battery considerations, it quickly has become equally important to powerline applications due to the cooling costs. Today, CPUs define a power constraint called Thermal Design Power (TDP) for the market it operates. One of the definition... » read more

Executive Insight: Wally Rhines
By Ann Mutschler - 05 May, 2014 - Comments: 1

Semiconductor Engineering sat down with Wally Rhines, chairman and CEO of Mentor Graphics, to discuss what is required for EDA to grow, key areas of opportunity for EDA growth and going against the grain. The interview is part of an ongoing series of in-depth interviews with top executives from all segments of the industry. SE: What keeps you awake at night? Rhines: Actually nothing keeps... » read more

A Guide To Advanced Process Design Kits
By Ernest Worthman - 14 Apr, 2014 - Comments: 1

The increasing complexity of design enablement has prompted manufacturers to optimize the design process. New tools and techniques, thanks to next-generation hardware and software, have provided a new platform for semiconductor and wafer design. Advanced PDKs are the solution and have been developed by foundries to optimize the design process and leverage and reuse intellectual property (IP) an... » read more

Executive Insight: Simon Davidmann
By Brian Bailey - 10 Apr, 2014 - Comments: 0

Every industry has some colorful characters and within the EDA industry, Simon Davidmann is certainly one that comes to mind. For the past 30-something years, Davidmann has provided guidance to the industry, stood up for what he believes in, been an inspiration to many entrepreneurs, and had some fun along the way. Simon is a serial entrepreneur, angel investor and he has been a key person invo... » read more

Pain Management
By Ed Sperling - 10 Apr, 2014 - Comments: 0

In part one of this series, the focus was on overlapping and new pain points in the semiconductor flow, from initial conception of what needs to be in a chip all the way through to manufacturing. Part two looks at how companies are attempting to manage that pain. It’s no secret that [getkc id="81" kc_name="SoC"]s are getting more complicated to design, debug and build, but the complexity i... » read more

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