tag: Eindhoven University of Technology

Blog Review: Oct. 13
By Jesse Allen - 13 Oct, 2021 - Comments: 0

Cadence's Paul McLellan checks out what Google learned in developing multiple generations of its TPU processor, including unequal advancement of logic and memory, the importance of compiler of compatibility, and designing for total cost of ownership. Siemens EDA's Jake Wiltgen argues for the importance of linting as part of eliminating systematic failures in designs complying with ISO 26262.... » read more

Manufacturing Bits: Aug. 24
By Mark LaPedus - 24 Aug, 2021 - Comments: 0

Panel packaging consortium Fraunhofer Institute for Reliability and Microintegration IZM has provided an update on a consortium that is developing panel-level IC packaging technologies. Fraunhofer IZM is leading the consortium. The R&D organization and its partners, including Intel and others, have made progress in terms of equipment, processes and other technologies in the so-called Pa... » read more

Manufacturing Bits: March 23
By Mark LaPedus - 23 Mar, 2021 - Comments: 0

Measuring acceleration The National Institute of Standards and Technology (NIST) has developed a new and better way to measure acceleration. NIST has developed an optomechanical accelerometer, a technology that has more resolution and bandwidth than conventional accelerometers. Optomechanical accelerometers uses laser light of a known frequency to measure acceleration. With the technology, ... » read more

Manufacturing Bits: Aug. 10
By Mark LaPedus - 10 Aug, 2020 - Comments: 0

EUV mask cleaning process TSMC has developed a new dry-clean technology for photomasks used in extreme ultraviolet (EUV) lithography, a move that appears to solve some major problems in the fab. TSMC and Samsung are in production with EUV lithography at advanced nodes, but there are still several challenges with the photomasks and other parts of the technology. Using 13.5nm wavelengths, EUV... » read more

Power/Performance Bits: May 19
By Jesse Allen - 19 May, 2020 - Comments: 0

Neuromorphic magnetic nanowires Researchers from the University of Texas at Austin, University of Texas at Dallas, and Sandia National Laboratory propose a neuromorphic computing method using magnetic components. The team says this approach can cut the energy cost of training neural networks. "Right now, the methods for training your neural networks are very energy-intensive," said Jean Ann... » read more

Power/Performance Bits: May 11
By Jesse Allen - 11 May, 2020 - Comments: 0

Light-emitting silicon Researchers from the Eindhoven University of Technology, Friedrich-Schiller-Universität Jena, Johannes Kepler University, and Technische Universität München developed a silicon germanium alloy that can emit light, paving the way for a silicon laser that could be integrated for on-chip and chip-to-chip communication. Bulk silicon is extremely inefficient at emitting... » read more

COVID-19 Tech Bits
By Linda Christensen - 06 Apr, 2020 - Comments: 0

Tech companies, consortiums and universities are jumping in to help fight COVID-19, deploying everything from massive computing capabilities to developing new technologies that can protect medical workers and first responders. Nearly all of these have ramped up over the past several weeks, as the tech world begins to take on a global challenge to combat the deadly virus. Compute resources... » read more

Manufacturing Bits: Feb. 18
By Mark LaPedus - 18 Feb, 2020 - Comments: 0

Molecular layer etch The U.S. Department of Energy’s Argonne National Laboratory has made new advances in the field of molecular layer etching or etch (MLE). MLE is related to atomic layer etch (ALE). Used in the semiconductor industry, ALE selectively removes targeted materials at the atomic scale without damaging other parts of the structure. ALE is related to atomic layer deposition... » read more

Testing In Context Gaining Ground
By Jeff Dorsch - 10 Dec, 2019 - Comments: 0

Testing in context is beginning to gain wider appeal as chip complexity increases, and as ICs are deployed in more safety-critical and mission-critical applications. While design in context has been the norm for SoCs for some time, a similar approach in test has been slow going. Cell-aware testing technology was first described a decade ago, and since then its adoption has been modest. But w... » read more

Blog Review: Dec. 4
By Jesse Allen - 04 Dec, 2019 - Comments: 0

Arm's Rupal Gandhi digs into the Cell-Aware Test methodology to deterministically target the growing number of defects that occur within the cells, the process of CAT library generation, and compares the static and transition patterns generated. Cadence's Paul McLellan shares highlights from the recent WOSET event with a look at the big drivers for the current interest in open-source EDA too... » read more

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