tag: electromigration

All Indicators Point North
By Ed Sperling - 28 Jun, 2012 - Comments: 0

Designing and producing chips has always been difficult, but the number of things that conspire to make it harder at 20nm is the longest in the history of the semiconductor industry. The list will grow longer still at 14nm and beyond, not to mention so expensive that one mistake will kill a company. While system engineers and architects look at the challenges on the front end, the problems ... » read more

New Reliability Issues
By Arvind Vel - 14 Jun, 2012 - Comments: 0

By Arvind Shanmugavel Reliability of ICs is a topic of growing concern with every technology node migration. With the onset of the 20nm process node from different foundries, reliability verification has taken center stage in design kits—and for good reason. Reliability margins have continued to decrease and have reached an inflection point at the 20nm node. The design and EDA communities ha... » read more

Power And Signal Line Electromigration Design And Reliability Validation Challenges
By Various Writers - 14 Jun, 2012 - Comments: 0

This white paper describes EM integrity analysis for power and signal lines. It outlines the various process and design trends that are increasing the likelihood of EM-induced failures in a design and looks at conventional verification techniques for EM integrity and contrasts those with what is required for advanced process nodes. To download this paper, click here. » read more

Tech Talk: Power Issues Ahead
By Ed Sperling - 31 May, 2012 - Comments: 0

Aveek Sarkar, vice president of technology and support at ANSYS Apache, talks with Low-Power Engineering about growing concerns over electrostatic discharge, electromigration, the impact of stacked die, and the need for power and thermal models. [youtube vid=-7TtszsuZP0] » read more

Old Problem, New Solutions
By Ed Sperling - 10 May, 2012 - Comments: 0

By Ann Steffora Mutschler Electromigration (EM) and electrostatic discharge (ESD) may not be new, but design design sophistication and tiny wires are demanding that engineering teams take a fresh look and utilize new tools to lesson the impacts of damaging electrical events. “These are certainly not new phenomenon,” said Carey Robertson, director of product marketing for Calibre at Ment... » read more

Extraction, Power And Final Silicon
By Ed Sperling - 12 May, 2011 - Comments: 0

By Ann Steffora Mutschler As semiconductor technology scales down, manufacturing effects are coming front and center, putting constant pressure on design teams to make sure that silicon can be modeled through the extraction process while performing analysis accurately. Extraction technology is one of the basic components needed to gain an accurate measurement of power, timing and signal int... » read more

The Growing Problem With Parasitic Extraction
By Ed Sperling - 11 Feb, 2010 - Comments: 0

By Ed Sperling Like everything else in semiconductor engineering at advanced process geometries, parasitic extraction is getting much more difficult at each node. There’s more circuit data to analyze, less distance between wires and much more to sort through. In addition, a 10% error in accuracy at 90nm might have been tolerable, while at 28nm it can completely change how a chip works. ... » read more

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