tag: EUV

Good Filters, Poor Resists
By Katherine Derbyshire - 14 Sep, 2016 - Comments: 0

Shrinking feature sizes and more complex lithography schemes are increasing the pressure on all aspects of the lithography process, including resists and resist filtration. As Clint Haris, vice president and general manager for liquid micro contamination control at Entegris explained, fabs are pushing resist manufacturers toward more stringent control of both contaminants and “soft particl... » read more

Speeding Up Mask Production
By Mark LaPedus - 12 Sep, 2016 - Comments: 0

Chip production is becoming more complex and expensive at each node. As a result, chipmakers require a growing number of new manufacturing technologies to enable the next wave of devices at advanced nodes. In the fab, for example, the most obvious need is extreme ultraviolet ([gettech id="31045" comment="EUV"]) lithography. In addition, chipmakers also need a new class of atomic-level proces... » read more

How Small Will Transistors Go?
By Mark LaPedus - 18 Aug, 2016 - Comments: 1

By Mark LaPedus & Ed Sperling There is nearly universal agreement that Moore’s Law is slowing down. But whether it will truly end, or just become too expensive and less relevant—and what will supplant device scaling—are the subject of some far-reaching research and much discussion. Semiconductor Engineering sat down with each of the leaders of three top research houses—[getent... » read more

Mask Maker Worries Grow
By Mark LaPedus - 18 Aug, 2016 - Comments: 2

Leading-edge photomask makers face a multitude of challenges as they migrate from the 14nm node and beyond. Mask making is becoming more challenging and expensive at each node on at least two fronts. On one front, mask makers must continue to invest in the development of traditional optical masks at advanced nodes. On another front, several photomask vendors are preparing for the possible ra... » read more

What Transistors Will Look Like At 5nm
By Mark LaPedus - 18 Aug, 2016 - Comments: 3

Chipmakers are currently ramping up 16nm/14nm finFET processes, with 10nm and 7nm just around the corner. The industry also is working on 5nm. TSMC hopes to deliver a 5nm process by 2020. GlobalFoundries, Intel and Samsung are doing R&D for that node. But 5nm technology presents a multitude of unknowns and challenges. For one thing, the exact timing and specs of 5nm remain cloudy. The... » read more

5 Takeaways From Semicon
By Mark LaPedus - 21 Jul, 2016 - Comments: 0

As usual, the recent Semicon West trade show was a busy, if not an overwhelming, event. The event, which took place in San Francisco in early July, featured presentations on the usual subjects in the semiconductor and IC-equipment sectors. There were sessions on 200mm, next-generation processes, transistors, lithography, MEMS and many others. In no particular order, here are my five ta... » read more

Executive Insight: Aart de Geus
By Ed Sperling - 20 Jul, 2016 - Comments: 0

Aart de Geus, chairman and co-CEO of Synopsys, sat down with Semiconductor Engineering to discuss Moore's Law, the IoT, inflection points and how chip design will evolve in coming years. SE: We are in the middle of possibly one of the biggest transition points we’ve ever seen in this industry. How do you envision things shaking out? De Geus: There is no question that there is an enormou... » read more

Atomic Layer Etch Heats Up
By Mark LaPedus - 29 Jun, 2016 - Comments: 0

The atomic layer etch (ALE) market is starting to heat up as chipmakers push to 10nm and beyond. ALE is a promising next-generation etch technology that has been in R&D for the last several years, but until now there has been little or no need to use it. Unlike conventional etch tools, which remove materials on a continuous basis, ALE promises to selectively and precisely remove targete... » read more

Interconnect Challenges Rising
By Mark LaPedus - 27 Jun, 2016 - Comments: 1

Chipmakers are ramping up their 14nm finFET processes, with 10nm and 7nm slated to ship possibly later this year or next. At 10nm and beyond, IC vendors are determined to scale the two main parts of the [getkc id="185" kc_name="finFET"] structure—the transistor and interconnects. Generally, transistor scaling will remain challenging at advanced nodes. And on top of that, the interconnects ... » read more

Executive Insight: Aki Fujimura
By Mark LaPedus - 23 Jun, 2016 - Comments: 1

Aki Fujimura, chief executive of D2S, sat down with Semiconductor Engineering to look at the key issues in lithography and photomasks, as well as the changes taking place in the IC industry. What follows are excerpts of that conversation. SE: The semiconductor market is changing on several fronts. On one front, there is a wave of consolidation in the industry. And then there is a slowdown in... » read more

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