tag: hybrid bonding

Challenges In Stacking HBM
By Ed Sperling - 03 Sep, 2025 - Comments: 1

AI data centers are pushing for higher density in high-bandwidth memory. Today, the maximum number of layers that can be stacked is 8, but that increases to as many as 24 layers by 2030. The big challenge will be in the interconnects, and making sure the microbumps align. At 16 layers, the bump pitch will be less than 10 microns, and the dies will be thinner. Damon Tsai, head of product marketi... » read more

Manufacturing At The Limits
By Gregory Haley - 21 Aug, 2025 - Comments: 2

Hybrid bonding has been in production for several years, with mature flows capable of delivering robust yields using 10µm interconnects. At that scale, processes can tolerate hundreds of nanometers of overlay variation, modest differences in wafer bow, and particle sizes rivaling the interconnect height without catastrophic impact. Hybrid bonding is compatible with optical metrology, existing ... » read more

Transferable Hybrid Bonding Technique That Allows For High Integration Density In Advanced Packaging
By Brewer Science - 21 Aug, 2025 - Comments: 0

A technical paper titled "Hierarchical Multi-Layer and Stacking Vias with Novel Structure by Transferrable Cu/Polymer Hybrid Bonding for High Speed Digital Applications" was published by researchers at Industrial Technology Research Institute (ITRI) and Brewer Science. The paper demonstrates a "novel structure with hierarchical multi-layer stacking vias as well as transferred hybrid bonding,... » read more

Metrology Under Pressure: Detecting Defects in Fine-Pitch Hybrid Bonding
By Gregory Haley - 12 Aug, 2025 - Comments: 1

As advanced packaging pushes deeper into the sub-10µm realm, traditional inspection and metrology systems are being forced to evolve with it. Hybrid bonding, a critical enabler of vertical integration and 3D system performance, relies on exceptionally tight alignment and defect-free bonding surfaces. But as interconnect pitch shrinks, even nanometer-scale variations in height, tilt, or cont... » read more

3DICs: Atomic-Scale Behavior of Electromigration in Cu−Cu Joints (NYCU, ITRI)
By Technical Paper Link - 05 Aug, 2025 - Comments: 0

A new technical paper titled "In Situ Atomic-Scale Investigation of Electromigration Behavior in Cu–Cu Joints at High Current Density" was published by researchers at National Yang Ming Chiao Tung University (NYCU) and the Industrial Technology Research Institute (ITRI). Excerpt "Electromigration (EM) poses significant challenges to the reliability of miniaturized devices, particularly th... » read more

Nanoimprint-Based Dielectric Patterning for Fine-Pitch Hybrid Bonding (Seoul National Univ. of Science and Technology)
By Technical Paper Link - 30 Jul, 2025 - Comments: 0

A new technical paper titled "Hybrid Bonding with Polymeric Interlayer Dielectric Layers Patterned by Nanoimprint Lithography" was published by researchers at Seoul National University of Science and Technology. Abstract "Recent advancements in semiconductor technology have shifted the focus of innovation toward advanced packaging technologies featuring heterogeneous integration. Among thes... » read more

On-Die And In-Package Interconnects: eBook
By Bryon Moyer - 28 Jul, 2025 - Comments: 0

We live in the Information Age, but if information cannot get to where it's intended to go, it does no good. And the way information gets from here to there is through interconnects. This report focuses on different interconnect structures, such as lines, vias, buses, and networks-on-chip, and how they’re constructed. As always, we consider the design, test, reliability, and security impli... » read more

CMOS 2.0: Layered Logic For The Post-Nanosheet Era
By Gregory Haley - 24 Jul, 2025 - Comments: 0

The semiconductor industry has relied on a simple equation for more than five decades — shrink the transistor, pack more onto every wafer, and watch performance soar as costs plummet. While each new node delivered predictable gains in speed, power efficiency, and density, that formula is rapidly running out of steam. As transistors approach single-digit nanometer processes, manufacturing c... » read more

Examination Of Thermal Issues Related to Hybrid Bonding of 3D-Stacked HBM
By Technical Paper Link - 16 Jul, 2025 - Comments: 0

A new technical paper titled "Thermal Issues Related to Hybrid Bonding of 3D-Stacked High Bandwidth Memory: A Comprehensive Review" was published by researchers at Chungbuk National University. Abstract "High-Bandwidth Memory (HBM) enables the bandwidth required by modern AI and high-performance computing, yet its three dimensional stack traps heat and amplifies thermo mechanical stress. We... » read more

How Advanced Packaging Is Reshaping Inspection
By Gregory Haley - 10 Jul, 2025 - Comments: 0

As semiconductor devices continue advancing into more sophisticated packaging schemes, traditional optical inspection technologies are brushing up against physical and computational boundaries. The growing reliance on 2.5D and 3D integration, hybrid bonding, and wafer-level processes has made it much harder to detect defects consistently and early enough to protect yields. While optical insp... » read more

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