On-Die And In-Package Interconnects: eBook


We live in the Information Age, but if information cannot get to where it's intended to go, it does no good. And the way information gets from here to there is through interconnects. This report focuses on different interconnect structures, such as lines, vias, buses, and networks-on-chip, and how they’re constructed. As always, we consider the design, test, reliability, and security impli... » read more

CMOS 2.0: Layered Logic For The Post-Nanosheet Era


The semiconductor industry has relied on a simple equation for more than five decades — shrink the transistor, pack more onto every wafer, and watch performance soar as costs plummet. While each new node delivered predictable gains in speed, power efficiency, and density, that formula is rapidly running out of steam. As transistors approach single-digit nanometer processes, manufacturing c... » read more

Examination Of Thermal Issues Related to Hybrid Bonding of 3D-Stacked HBM


A new technical paper titled "Thermal Issues Related to Hybrid Bonding of 3D-Stacked High Bandwidth Memory: A Comprehensive Review" was published by researchers at Chungbuk National University. Abstract "High-Bandwidth Memory (HBM) enables the bandwidth required by modern AI and high-performance computing, yet its three dimensional stack traps heat and amplifies thermo mechanical stress. We... » read more

How Advanced Packaging Is Reshaping Inspection


As semiconductor devices continue advancing into more sophisticated packaging schemes, traditional optical inspection technologies are brushing up against physical and computational boundaries. The growing reliance on 2.5D and 3D integration, hybrid bonding, and wafer-level processes has made it much harder to detect defects consistently and early enough to protect yields. While optical insp... » read more

Wafer Bonding Mechanisms Using SiCN Films For Hybrid Bonding Applications In 3D Integration 


A new technical paper titled "Material-Mechanistic Interplay in SiCN Wafer Bonding for 3D Integration" was published by researchers at Yokohama National University, TEL, SK hynix, and University of Tsukuba. According to the paper: "Although much research has been conducted on wafer bonding methods compatible with the latest semiconductor manufacturing processes, discussions on the interface... » read more

On The Ground At ECTC 2025


Senior Executive Editor Laura Peters examines the the hot topics at last week's IEEE's Electronic Components and Technology Conference, including the impact of hardware-software integration on power consumption, co-packaged optics, hybrid bonding, and fan-out panel-level packaging. https://youtu.be/yBDKqrPQBl4   » read more

Transformation Of 2D-ICs Into 3D-ICs Using Shuttle Chips From Multi-Project Wafers (Tohoku University)


A new technical paper titled "Die-Level Transformation of 2D Shuttle Chips into 3D-IC for Advanced Rapid Prototyping using Meta Bonding" was published by researchers at Tohoku University. Abstract "Three-dimensional integrated circuit (3D-IC) technology, often referred to as through-silicon via (TSV) formation technology, has been steadily maturing and is increasingly used in advanced semic... » read more

Advanced Packaging Fundamentals for Semiconductor Engineers: eBook


Advanced packaging is inevitable. Large systems companies and processing vendors already are working with various types of highly engineered packaging. The rest of the semiconductor industry will follow at some point, whether they're designing their own packages, developing the tools, processes, materials, and methodologies to create them, or developing components that will be used inside of th... » read more

Benefits And Challenges In Multi-Die Assemblies


Experts at the Table: Semiconductor Engineering sat down to discuss chiplets, hybrid bonding, and new materials with Michael Kelly, vice president of Chiplets and FCBGA Integration at Amkor; William Chen, fellow at ASE; Dick Otte, CEO of Promex Industries; and Sander Roosendaal, R&D director at Synopsys Photonics Solutions. What follows are excerpts of that discussion. To view part one of t... » read more

Thermal Analysis Of 3D Stacking And BEOL Technologies With Functional Partitioning Of Many-Core RISC-V SoC


Thermal challenges in 3D-IC designs can cause a significant risk in meeting performance specifications. While the pace of Moore’s Law has slowed in recent years, system technology co-optimization (STCO) promises to mitigate technology scaling bottlenecks with system architecture tuning based on emerging technology offerings, including 3D technology. This white paper analyzes the impact of mat... » read more

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