Transferable Hybrid Bonding Technique That Allows For High Integration Density In Advanced Packaging


A technical paper titled "Hierarchical Multi-Layer and Stacking Vias with Novel Structure by Transferrable Cu/Polymer Hybrid Bonding for High Speed Digital Applications" was published by researchers at Industrial Technology Research Institute (ITRI) and Brewer Science. The paper demonstrates a "novel structure with hierarchical multi-layer stacking vias as well as transferred hybrid bonding,... » read more

Metrology Under Pressure: Detecting Defects in Fine-Pitch Hybrid Bonding


As advanced packaging pushes deeper into the sub-10µm realm, traditional inspection and metrology systems are being forced to evolve with it. Hybrid bonding, a critical enabler of vertical integration and 3D system performance, relies on exceptionally tight alignment and defect-free bonding surfaces. But as interconnect pitch shrinks, even nanometer-scale variations in height, tilt, or cont... » read more

3DICs: Atomic-Scale Behavior of Electromigration in Cu−Cu Joints (NYCU, ITRI)


A new technical paper titled "In Situ Atomic-Scale Investigation of Electromigration Behavior in Cu–Cu Joints at High Current Density" was published by researchers at National Yang Ming Chiao Tung University (NYCU) and the Industrial Technology Research Institute (ITRI). Excerpt "Electromigration (EM) poses significant challenges to the reliability of miniaturized devices, particularly th... » read more

Nanoimprint-Based Dielectric Patterning for Fine-Pitch Hybrid Bonding (Seoul National Univ. of Science and Technology)


A new technical paper titled "Hybrid Bonding with Polymeric Interlayer Dielectric Layers Patterned by Nanoimprint Lithography" was published by researchers at Seoul National University of Science and Technology. Abstract "Recent advancements in semiconductor technology have shifted the focus of innovation toward advanced packaging technologies featuring heterogeneous integration. Among thes... » read more

On-Die And In-Package Interconnects: eBook


We live in the Information Age, but if information cannot get to where it's intended to go, it does no good. And the way information gets from here to there is through interconnects. This report focuses on different interconnect structures, such as lines, vias, buses, and networks-on-chip, and how they’re constructed. As always, we consider the design, test, reliability, and security impli... » read more

CMOS 2.0: Layered Logic For The Post-Nanosheet Era


The semiconductor industry has relied on a simple equation for more than five decades — shrink the transistor, pack more onto every wafer, and watch performance soar as costs plummet. While each new node delivered predictable gains in speed, power efficiency, and density, that formula is rapidly running out of steam. As transistors approach single-digit nanometer processes, manufacturing c... » read more

Examination Of Thermal Issues Related to Hybrid Bonding of 3D-Stacked HBM


A new technical paper titled "Thermal Issues Related to Hybrid Bonding of 3D-Stacked High Bandwidth Memory: A Comprehensive Review" was published by researchers at Chungbuk National University. Abstract "High-Bandwidth Memory (HBM) enables the bandwidth required by modern AI and high-performance computing, yet its three dimensional stack traps heat and amplifies thermo mechanical stress. We... » read more

How Advanced Packaging Is Reshaping Inspection


As semiconductor devices continue advancing into more sophisticated packaging schemes, traditional optical inspection technologies are brushing up against physical and computational boundaries. The growing reliance on 2.5D and 3D integration, hybrid bonding, and wafer-level processes has made it much harder to detect defects consistently and early enough to protect yields. While optical insp... » read more

Wafer Bonding Mechanisms Using SiCN Films For Hybrid Bonding Applications In 3D Integration 


A new technical paper titled "Material-Mechanistic Interplay in SiCN Wafer Bonding for 3D Integration" was published by researchers at Yokohama National University, TEL, SK hynix, and University of Tsukuba. According to the paper: "Although much research has been conducted on wafer bonding methods compatible with the latest semiconductor manufacturing processes, discussions on the interface... » read more

On The Ground At ECTC 2025


Senior Executive Editor Laura Peters examines the the hot topics at last week's IEEE's Electronic Components and Technology Conference, including the impact of hardware-software integration on power consumption, co-packaged optics, hybrid bonding, and fan-out panel-level packaging. https://youtu.be/yBDKqrPQBl4   » read more

← Older posts Newer posts →