Extending Portable Stimulus


It has been a year since Accellera's Portable Test and Stimulus Specification became a standard. Semiconductor Engineering sat down to discuss the impact it has had, and the future direction of it, with Larry Melling, product management director for Cadence; Tom Fitzpatrick, strategic verification architect for Mentor, a Siemens Business; Tom Anderson, technical marketing consultant for OneSpin... » read more

Week In Review: Manufacturing, Test


Fab tools A consortium of 31 companies have launched a new project, called the “Advanced packaging for photonics, optics and electronics for low cost manufacturing in Europe.” The program is referred to as APPLAUSE. With a budget of 34 million euros, the project is being coordinated by ICOS, a division of KLA. “APPLAUSE will focus on advanced optics, photonics and electronics packagin... » read more

Making Better Use Of Memory In AI


Steven Woo, Rambus fellow and distinguished inventor, talks about using number formats to extend memory bandwidth, what the impact can be on fractional precision, how modifications of precision can play into that without sacrificing accuracy, and what role stochastic rounding can play. » read more

Power Modeling Standard Released


Power is becoming a more important aspect of semiconductor design, but without an industry standard for power models, adoption is likely to be slow and fragmented. That is why Si2 and the IEEE decided to do something about it. Back in 2014, the IEEE expanded its interest in power standards with the creation of two new groups IEEE P2415 - Standard for Unified Hardware Abstraction and Layer fo... » read more

Week in Review: IoT, Security, Autos


Products/Services Siemens announced that Mazda Motor adopted the Capital electrical design software suite from Mentor, a Siemens Business, for the design of next-generation automotive electrical systems. Mazda is said to use Capital for model-based generative design for the electrical and electronic systems of the entire vehicle platform. Synopsys will host the 11th annual Codenomi-con USA ... » read more

Week In Review: Design, Low Power


Si2's Unified Power Model has been approved as IEEE 2416-2019, a new Standard for Power Modeling to Enable System Level Analysis, which complements UPF/IEEE 1801-2018. UPM/IEEE 2416-2019 provides a set of power modeling semantics enabling system designers to model entire systems with flexibility. It supports power modeling from abstract design description to gate level implementation, providing... » read more

System Bits: July 3


CMU prof gets a shot at new supercomputer The National Energy Research Scientific Computing Center will greet its Perlmutter supercomputing system in early 2020. The Cray-designed machine will be capable of 100 million billion floating operations per second. Zachary Ulissi of Carnegie Mellon University will be among the first researchers to use the supercomputer. "When this machine comes on... » read more

Manufacturing Bits: June 25


Panel-level consortium Fraunhofer is moving forward with the next phase of its consortium to develop technologies for panel-level packaging. In 2016, Fraunhofer launched the original effort, dubbed the Panel Level Packaging Consortium. The consortium, which had 17 partners, developed various equipment and materials in the arena. Several test layouts were designed for process development on ... » read more

Telle Whitney Receives IEEE Honorary Membership


On May 17 Telle Whitney received the 2019 IEEE Honorary Membership at the 2019 IEEE Vision, Innovation, and Challenges Summit (IEEE VIC Summit) in San Diego for leadership in supporting and promoting women in technology, and for building a highly impactful global organization dedicated to this purpose. Sponsored by IEEE, the grade of Honorary Member is a significant honor bestowed by IEEE a... » read more

Manufacturing Bits: June 10


Predicting warpage in packages At the recent IEEE Electronic Components and Technology Conference (ECTC) in Las Vegas, there were several papers on ways to predict variation and warpage in IC packages. Advanced packages are prone to unwanted warpage during the process flow. The warpage challenges escalate as the packages become thinner. Warpage in turn can impact yields in IC packages. ... » read more

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