Where Technology Breakthroughs Are Needed

Gaps are emerging everywhere, from interconnects and memories to materials and manufacturing.


After years of delays, extreme ultraviolet (EUV) lithography is finally in production at the 7nm logic node with 5nm in the works.

EUV, a next-generation lithography technology, certainly will help chipmakers migrate to the next nodes. But EUV doesn’t solve every problem. Nor does it address all challenges in the semiconductor industry. Not by a long shot.

To be sure, the industry needs new breakthroughs in several areas, such as memories, packaging, power semis and transistors. These will require new device architectures and materials, as well as tools besides EUV.

This, of course, has been known for some time. But this became even more evident during a panel at the recent IEEE International Electron Devices Meeting (IEDM). Hosted by Applied Materials, the panel was entitled: “The Future of Logic—EUV is Here, Now What?”

At the event, the panelists described several technologies that require new breakthroughs or will at least help propel Moore’s Law. Then, at other events during the year, many experts have talked about different technologies that also need to be addressed.

The list of required technology breakthroughs is almost endless. In no particular order, here’s just a few of the main ones:

Transistor, interconnect breakthroughs
A leading-edge chip consists of three parts—the transistor, contacts and interconnects. The transistor resides on the bottom of the structure and serves as a switch. The interconnects, which reside on the top of the transistor, consist of tiny copper wiring schemes that transfer electrical signals from one transistor to another.

The transistor structure and interconnects are connected by a layer called the middle-of-line (MOL). The MOL layer consists of a series of tiny contact structures.

There some challenges here. “Once we have EUV, that actually opened the door that we need to solve a lot more issues,” said Geoffrey Yeap, senior director of advanced technology at TSMC, during the panel at IEDM. “Dynamic power constantly needs to be reduced. We need to pay more attention about low Vdd operation efficiency. Ultimately, we also need a better transistor, a more energy efficient and high-performance transistor.”

For some time, the biggest challenge in chip scaling involves the copper interconnects. The interconnects are becoming more compact at each node, causing an unwanted resistance-capacitance (RC) delay in chips.

For years, the industry has used the same process to make the copper interconnects. Changes in the materials have been evolutionary.

To make these structures, chipmakers use traditional lithography, along with deposition and etch. Going forward, EUV will help simplify the process.

But that’s not enough. RC delay isn’t going away. All told, the industry needs new materials in the interconnects. It perhaps needs some revolutionary changes, even a copper replacement.

“So ultimately, I still say the biggest question is still the interconnect, resistance and capacitance. When I say interconnect, it’s not just the backend. I also mean the middle-of-line,” Yeap said.

The MOL is also challenging. Some chipmakers have moved to new materials for the MOL contacts. Time will tell if that’s the right path.

New chip and AI architectures
For some time, Gary Dickerson, chief executive of Applied Materials, has stated that the semiconductor industry needs a “new playbook.”

With Moore’s Law slowing down, the “playbook” involves a new class of chip architectures, rather than the traditional ones. This requires new techniques to drive power, performance, area and cost (PPAC).

The industry needs to think differently. “We have been working on mobile and social media for quite a long time. Right now, we are moving into AI and big data. With this change comes a lot of opportunities, but also a chance to look at what we should do different for these applications,” said Regina Freed, managing director of patterning technology development at Applied Materials, during the panel.

In simple terms, the playbook includes new architectures, materials, 3D structures and advanced packaging. The industry needs new ways to continue 2D scaling.

AR/VR breakthroughs
For some time, Facebook has sold virtual reality (VR) headsets, which enable users to experience 3D virtual environments. Augmented reality (AR) takes computer-generated images and overlays them on the system, according to Facebook.

In R&D, Facebook is developing new technologies, including next-generation AR glasses. “We can imagine a lot of functions. For example, it could allow to have a whiteboard in a business meeting, which is done in remote. Or it could even project our workplace, for example, in a plane,” said Barbara De Salvo, a silicon technology strategist at Facebook, during the panel.

To develop this system, the company requires new breakthroughs in various areas, such as AI, chips, computer vision, displays and interfaces.

“This is extremely difficult at the level of a full system,” De Salvo said. “I don’t think that what we are seeing today in the market is satisfying the needs to really achieve this goal. The power requirements are really well beyond what exists today. So we have to find the solution.”

Simply put, the industry needs ultra low-power chip architectures, better next-generation memories and microLEDs.

Advances in advanced packaging
Traditional chip scaling is becoming more difficult and expensive at each node. So, the industry is searching for alternatives. Another way to get the benefits of scaling is by putting multiple and complex chips in an advanced package.

“Packaging technology is increasingly important,” said Ramune Nagisetty, director of process and product integration at Intel, during the panel.

Chiplets is another idea. In chiplets, the idea is that you have a menu of modular chips, or chiplets, in a library. Then, you integrate them in a package using a die-to-die interconnect scheme.

“The future is about specialization at scale with advanced packaging and interoperable chiplets,” Nagisetty said. “I believe that in the future, an industry scale ecosystem will evolve around these concepts of a chiplet library, where you have different technology nodes. This is where you can swap out an older technology node for a new technology node, for example, for your high-speed cores. And then, you have specialized nodes for specific functionality like power delivery, memory or specific types of accelerators like GPUs.”

But there are a number of challenges. Advanced packaging is still expensive. Some processes are slow and costly. The integration of chiplets also presents some issues.

Memory replacements
For years, the industry has been developing several next-generation memory types that could replace DRAM and flash.

Planar NAND flash is slow and running out of steam. Fortunately, the industry found a solution to replace today’s planar NAND—3D NAND.

DRAM, meanwhile, is a power-hungry device that is reaching its physical limit. Many want a DRAM replacement. The industry is working on various new memory types to displace DRAM, but there is no replacement yet.

“At this time, we cannot see any next-gen type of memory that can directly replace DRAM,” said David Hideo Uriu, product marketing director at UMC, in a recent e-mail exchange. “We do see an SRAM replacement through the use of MRAM. But for the goal of a persistent DRAM replacement, we can only see a ‘hybrid cached’ DRAM/MRAM component.”

Others agree. “Emerging memory is not expected to impede significantly on existing NAND or DRAM markets over the next 5-10 years as standalone products,” said Scott Hoover, principal yield consultant at KLA, in a separate exchange. “MRAM could be a future DRAM replacement due to latency and selector similarities, but it’s difficult to scale >10GB and is not quite as fast as DRAM in reality.”

A DRAM replacement will require new architectures and materials. There are many new ideas, at least on the drawing board.

New power semis
Power semiconductors operate as a switch in high-voltage applications such as automotive, power supplies, solar and trains. The devices allow the electricity to flow in the “on” state and stop it in the “off” state. They boost the efficiencies and minimize the energy losses in systems.

For years, the power semi market has been dominated by silicon-based devices. Based on older nodes, silicon-based power semis are inexpensive, but they are also reaching their theoretical limits in several respects.

Power semiconductors based on gallium nitride (GaN) and silicon carbide (SiC) promise to solve those issues. Both GaN and SiC are wide-bandgap technologies, meaning they are more efficient than silicon-based devices. They also have a higher breakdown field and a higher thermal conductivity than silicon.

GaN and SiC power semis have made inroads, but both face several challenges. “Despite the early stage success of SiC, there are still many technical challenges that need to be addressed for the technology to reach its full market potential. Substrate cost, availability and quality are still a challenge,” said David Haynes, senior director of strategic marketing at Lam Research, in a recent exchange.

GaN power semis also have some challenges, such as device performance and reliability.

More breakthroughs
This is by no means a complete list. The industry needs breakthroughs in other apps, such as AI, autonomous driving, batteries, displays, quantum computing and others. Then, on the fab tool side, chipmakers want new selective deposition equipment, inspection/metrology systems and other gear.

To be sure, chip scaling isn’t going away. EUV is needed. There is a need for leading-edge chips in select applications, such as servers and smartphones. Then, a plethora of new AI chip startups are surfacing. Many are designing chips for machine learning and deep learning. “There’s no question that being able to compute 10x faster than now will be commercially useful and competitively required, even for non-technical markets. All of deep learning’s unique accomplishments are evidence of that. There’s virtually no end in sight for the demand for more computing power,” said Aki Fujimura, chief executive of D2S.

But it’s also refreshing to have so many new and intriguing technologies in new markets.

Related Stories
Power Semi Wars Begin
They won’t replace silicon, but GaN and SiC are becoming much more attractive as prices drop.
What’s The Best Advanced Packaging Option?
A dizzying array of choices and options pave the way for the next phase of scaling.
Building An MRAM Array
Why MRAM is so attractive.
Advanced Packaging Options Increase
But putting multiple chips into a package is still difficult and expensive.


guest says:

EUV didn’t solve these problems and certainly added its own, particularly stochastics and uptime.

Rod'57 says:

Is SiC “faster and more efficient than silicon-based devices” (like GaN) ? or is it just able to tolerate higher voltages and temperatures and hence handle higher powers ?

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