Blog Review: Apr. 15


Cadence's Wilson Kobalkar shares why eUSB2‑V2 represents a major evolutionary step for the USB 2.0 ecosystem, including how it achieves multi‑gigabit HSx operation and why symmetric/asymmetric modes unlock new design possibilities. Synopsys' Akanksha Soni explains the difference between metal-oxide-metal, metal-insulator-metal, and metal-oxide-semiconductor capacitors, identifying the ad... » read more

Chip Industry Week In Review


Deals, Funding Intel will join Elon Musk’s Terafab chip manufacturing project alongside Tesla, SpaceX, and xAI. Intel described its role as helping refactor silicon fab technology for a project targeting production of 1 TW/year of compute for AI and robotics applications. Intel and Google are expanding a multi-year collaboration on AI and cloud infrastructure, with Intel Xeon processo... » read more

Chip Industry Week In Review


Deals IBM and Arm are collaborating on a new dual‑architecture hardware aimed at enterprise AI and data-intensive workloads, using virtualization to boost reliability, security, scalability, and software compatibility. The goal, according to an IBM spokesperson, is to deliver side-by-side deployments of S390x-Linux and Arm-Linux virtual machines in a single kernel-based hypervisor. Nv... » read more

Challenges In Scaling Chips To 2nm And Below


Key Takeaways Scaling to 2nm and below continues due to power improvements per watt, but progress is much more challenging and costly. Solutions to problems often create other problems due to less margin for tradeoffs, often requiring larger interposers, more chiplets, and more complex packages. New levels of precision are required throughout the design-through-manufacturing flow, re... » read more

Chip Industry Week In Review


Big Deals and Fundings Rapidus secured US$1.7B in a new funding round from the Japanese government and the private sector to ramp 2nm production by next year. Open AI announced a $110B in new funding, with $30B from Nvidia, $30B from Softbank and $50B from Amazon. In a $100B multi-year deal, Meta will power its AI infrastructure with up to 6GW of AMD's GPUs. SambaNova and Intel ar... » read more

Backside Power Delivery Creates Fab Tool, Thermal Dissipation Barriers


Key Takeaways Backside power delivery reduces routing congestion at the most advanced nodes and offers significant performance improvement options. But it also adds a bunch of new challenges involving via alignment and interconnects. Still, leading-edge foundries are making progress, and all of them plan to offer BPDNs at 2nm and below. Backside power delivery networks deliv... » read more

Chip Industry Week in Review


Intel hired ex-Qualcomm GPU guru Eric Demers for the company's high-performance GPU push, setting the stage for a three-way battle with Nvidia and AMD. The key targets for Intel and AMD will be better power efficiency and a programming model that rivals CUDA, but don't expect Nvidia to stand still. Acquisitions Texas Instruments plans to acquire Silicon Labs for ~$7.5B cash to enhance i... » read more

Why Move To 2nm?


Key Takeaways: Scaling digital logic still provides significant benefits, especially lower power. Multi-die assemblies will be the predominant approach, and most of the circuitry will not be 2nm or below. While these systems are inherently more flexible, the number and complexity of tradeoffs required for optimizing PPA/C are increasing. The rollout of 2nm process nodes and ... » read more

More Data, More Redundant Interconnects


The proliferation of AI dramatically increases the amount of data that needs to be processed, stored, and moved, accelerating the aging of signal paths through which that data travels and forcing chipmakers to build more redundancy into the interconnects. In the past, nearly all redundant data paths were contained within a planar chip using a relatively thick silicon substrate. But as chipma... » read more

Three-Way Race To 3D-ICs


Intel Foundry, TSMC, and Samsung Foundry are scrambling to deliver all the foundational components of full 3D-ICs, which collectively will deliver orders of magnitude improvements in performance with minimal power sometime within the next few years. Much attention has been focused on process node advances, but a successful 3D-IC implementation is much more complex and comprehensive than just... » read more

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